Microprogrammed CPU
1
Computer Organization and Architecture
Course Design
NAME:
STUDENT No.:
COURSE:
PROJECT:
DATE:
Microprogrammed CPU
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1. Purpose
The purpose of this project is to design a simple CPU (Central Processing Unit). This
CPU has basic instruction set, and we will utilize its instruction set to generate a very
simple program to verify its performance. For simplicity, we will only consider the
relationship among the CPU, registers, memory and instruction set. That is to say we
only need consider the following items: Read/Write Registers, Read/Write Memory
and Execute the instructions.
At least four parts constitute a simple CPU: the control unit, the internal registers,
the ALU and instruction set, which are the main aspects of our project design and
will be studied.
2. Instruction Set
Single-address instruction format is used in our simple CPU design. The instruction
word contains two sections: the operation code (opcode), which defines the function
of instructions (addition, subtraction, logic operations, etc.); the address part, in
most instructions, the address part contains the memory location of the datum to be
operated, we called it direct addressing. In some instructions, the address part is the
operand, which is called immediate addressing.
For simplicity, the size of memory is 256× 16 in the computer. The instruction word
has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction
word format can be expressed in Figure 4
The opcode of the relevant instructions are listed in Table 1.
In Table 1, the notation [x] represents the contents of the location x in the memory.
For example, the instruction word 00000011101110012 (03B916) means that the CPU
adds word at location B916 in memory into the accumulator (ACC); the instruction
word 00000101000001112 (050716) means if the sign bit of the ACC (ACC [15]) is 0,
the CPU will use the address part of the instruction as the address of next instruction,
if the sign bit is 1, the CPU will increase the program counter (PC) and use its content
as the address of the next instruction.
Figure 1
Microprogrammed CPU
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All the instructions except the Division instruction must be supported in your design.
It is better if you can implement the instruction: DIV X. Also, you can design more
instructions if needed.
You must design several programs to test these instructions. A program is given as
an example:
Calculate the sum of all integers from 1 to 100.
1. Programming with C language:
sum=0;
temp=100;
loop :sum=sum+temp;
temp=temp-1;
if temp>=0 goto loop;
end
2. Assume in the memory:
sum is stored at location A4,
temp is stored at location A3,
the contents of location A0 is 0,
the contents of location A1 is 1,
the contents of location A2 is 10010=6416.
We can translate the above C language program with the instructions listed in Table
1 into the instruction program as shown in Table 2.
Microprogrammed CPU
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3. Internal Registers and Memory
MAR (Memory Address Register)
MAR contains the memory location of the word to be read from the memory or
written into the memory. Here, READ operation is denoted as the CPU reads from
memory, and WRITE operation is denoted as the CPU writes to memory. In our
design, MAR has 8 bits to access one of 256 addresses of the memory.
MBR (Memory Buffer Register)
MBR contains the value to be stored in memory or the last value read from memory.
MBR is connected to the address lines of the system bus. In our design, MBR has 16
bits.
PC (Program Counter)
PC keeps track of the instructions to be used in the program. In our design, PC has 8
bits.
Microprogrammed CPU
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IR (Instruction Register)
IR contains the opcode part of an instruction. In our design, IR has 8 bits.
BR (Buffer Register)
BR is used as an input of ALU; it holds other operand for ALU. In our design, BR has
16 bits.
ACC (Accumulator)
ACC holds one operand for ALU, and generally ACC holds the calculation result of
ALU. In our design, ACC has 16 bits.
MR (Multiplier Register)
MR is used for implementing the MPY instruction, holding the multiplier at the
beginning of the instruction. When the instruction is executed, it holds part of the
product.
DR (Division Register)
DR is used for implementing the DIV instruction, you can define it according to your
division algorithm.
LPM_RAM_DQ
LPM_RAM_DQ is a RAM with separate input and output ports, it works as memory,
and its size is 256× 16. Although it’s not an internal register of CPU, we need it to
simulate and test the performance of CPU.
All the registers are positive-edge-triggered.
All the reset signals for the registers are synchronized to the clock signal.
ALU
ALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic
and logic operations. In our design, some operations must be supported which are
listed as
follows
Microprogrammed CPU
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4. Microprogrammed Control Unit
Introduction
We have learnt the knowledge of Microprogrammed control unit. Here, we only
review some terms and basic structures.
In the Microprogrammed control, the microprogram consists of some
microinstructions and the microprogram is stored in control memory that generates
all the control signals required to execute the instruction set correctly. The
microinstruction contains some micro-operations which are executed at the same
time.
Microprogrammed CPU
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Figure 5 shows the key elements of such an implementation. The set of
microinstructions is stored in the control memory. The control address register
contains the address of the next microinstructions to be read. When a
microinstruction is read from the control memory, it is transferred to a control
buffer register. The register connects to the control lines emanating from the control
unit. Thus, reading a microinstruction from the control memory is the same as
executing that microinstruction. The third element shown in the figure is a
sequencing unit that loads the control address register and issues a read command.
Control Word Format
Figure 4 Control Word Format
A 32-bit Control Word is applied in the design, whose format is shown in Figure
4. The Control Word is mainly horizontal, with exception to the JUMP field, which
is designed vertically.
Microprogrammed CPU
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Field Function
Internal CPU Control Signals (bit 31-10) control bits for data path between
registers and memory
Jump Condition(bit 9-8) bits for the Virtual Branch * to
determine the Jump work
Address Field( bit 7-0) bits designates next
microinstruction’s address in the
Control Memory
Control Word Field and Function
Control word definition:
Bit Meaning
31~29 OP
28 Unused
27 Unused
26 C16, DRDR-1
25 C15, DRDR+1
24 C14, DR0
23 C13, ACC0
22 C12, ACCALU
21 C11, ALUACC
10 C10, ALUBR
19 C9, PCPC+1
18 C8, MARPC
17 C7, MRALU
16 C6, BRMBR
15 C5, IRMBR
14 C4, PCMBR
13 C3, MARMBR
12 C2, ACCMBR
11 C1, RAMMBR
10 C0, MBRRAM
8~9 JUMP CONDITION
0~7 ADDRESS FIELD
Jump condition:
00 no jump CARCAR+1;
01 unconditional jump, CARADDRESS FILED
10 jump according to opcode, CARADDRESS FIELD
11 conditional jump, if flag=0, CARADDRESS FIELD
Microprogrammed CPU
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OP:
000 ADD
001 SUB
010 MPY
011 AND
100 OR
101 NOT
110 SHL
111 SHR
Control Unit Structure.
For a micro-programmed CPU, Control Unit functions as providing with control
signals internal CPU registers and memory, as well as Control Unit itself,
according to the feedback signals and flags from without.
A Typical Design of Control Unit
Typically, the Control Unit must consist of the following elements: CAR, CBR,
Sequence Logic, Branch, Multiplexer and Control Memory. The architecture of
this kind of Control Unit is depicted in Figure 5.
This Control Unit works in the sequence described by the following figure.
Microprogrammed CPU
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To simplify the whole process and structure of microprogrammed control unit,
we combine the entire CAR, CBR and the like together. They are all included in
the chip”CU”. By connecting with ROM, it can exactly send out different
instructions.
CU ROM
Microprogrammed CPU
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5. CPU Design
Figure 6 indicates a simple CPU architecture and its use of a variety of internal data
paths and control signals. Our CPU design should be based on this architecture.
You should determine the control signals according to the CPU architecture you’re
your design. An example is given below to show the procedure, this example
describes the control unit design for the LOAD instruction.
First, we need determine the control flowchart of the LOAD instruction.
Microprogrammed CPU
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Microprogrammed CPU
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You can draw all of the control flowcharts for each instruction and determine corresponding
control signals descriptions.
The control memory can be implemented by ALTERA LPM_RAM_DQ in MAXPLUS software;
you can find reference from its help document or the APPENDIX.
Before you start to design, please refer to chapter 14 and chapter 15 of the textbook <>.
6. Overall connection:
Top level connection
VCC
clk INPUT
VCC
clk_1 INPUT
VCC
rst INPUT
O_MAR[7..0]OUTPUT
O_BR[15..0]OUTPUT
O_MR[15..0]OUTPUT
O_PC[7..0]OUTPUT
O_MBR[15..0]OUTPUT
O_DR[7..0]OUTPUT
data[15..0]
w ren
address[7..0]
clock
q[15..0]
lpm_ram_dq5
inst1
address[7..0]
clock
q[31..0]
lpm_rom3
inst2
RAM[15..0]
ROM[31..0]
clk
rst
ROM_ADR[7..0]
CLT[21..0]
O_ACC[15..0]
O_MAR[7..0]
O_ALU[15..0]
O_MBR[15..0]
O_BR[15..0]
O_IR[7..0]
O_MR[15..0]
O_DR[7..0]
FLG
O_PC[7..0]
cpu_1
inst
ROM_ADR[7..0]
clk_1
RAM[15..0]
CLT[1]
CLT[21..0]
ROM_ADR[7..0]
clk_1
rst
clk
RAM[15..0]
O_ACC[15..0]
O_MAR[7..0]
O_ALU[15..0]
O_BR[15..0]
O_IR[7..0]
O_MR[15..0]
O_DR[7..0]
O_PC[7..0]
FLAG
Microprogrammed CPU
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Internal connection of CPU
clk
c3
c8
rst
i_mbr[7..0]
i_pc[7..0]
opt[7..0]
MAR
inst
clk
c0
c2
rst
i_ram[15..0]
i_acc[15..0]
opt[15..0]
MBR
inst11
clk
rst
c10
c11
c14
c15
c16
acc_in[15..0]
br_in[15..0]
opcode[2..0]
output[15..0]
out_dr[7..0]
out_mr[15..0]
ALU
inst3
clk
c5
rst
i_mbr[7..0]
opt[7..0]
IR
inst14
CLT[10]
O_ACC[15..0]
O_BR[15..0]
CLT[14]
CLT[15]
CLT[16]
CLT[21..19]
CLT[11]
rst
clk O_ALU[15..0]
O_DR[7..0]
O_ALU_MR[15..0]
clk
CLT[3]
CLT[8]
rst
O_MBR[7..0]
O_PC[7..0]
O_MAR[7..0]
clk
CLT[0]
CLT[2]
rst
O_ACC[15..0]
RAM[15..0]
O_MBR[15..0]
clk
CLT[5]
rst
O_MBR[15..8]
O_IR[7..0]
clk
c4
c9
rst
i_mbr[7..0]
opt[7..0]
PC
inst12
clk
c12
c13
rst
i_alu[15..0]
f lg
opt[15..0]
ACC
inst15
clk
c6
rst
i_mbr[15..0]
opt[15..0]
BR
inst16
clk
c7
rst
i_mr[15..0]
opt[15..0]
MR
inst7
O_BR[15..0]clk
CLT[6]
rst
O_MBR[15..0]
CLT[12]
CLT[13]
clk
rst
O_ALU[15..0]O_MBR[7..0]
rst
CLT[9]
CLT[4]
clk FLG
O_ACC[15..0]
O_PC[7..0]
clk
CLT[7]
rst
O_MR[15..0]
O_ALU_MR[15..0]
CLT[21..0]OUTPUT
ROM_ADR[7..0]OUTPUTclk
rst
f lag
ir[7..0]
rom_csgn[21..0]
rom_cnd[1..0]
rom_adr[7..0]
out_adr[7..0]
out_csgn[21..0]
CU
inst8
ROM_ADR[7..0]
ROM_ADR[7..0]
clk
rst
FLG
O_IR[7..0]
ROM[31..10]
ROM[9..8]
ROM[7..0]
Microprogrammed CPU
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Connection of CU
CLT[21..0]OUTPUT
clk
rst
f lag
ir[7..0]
rom_csgn[21..0]
rom_cnd[1..0]
rom_adr[7..0]
out_adr[7..0]
out_csgn[21..0]
CU
inst8
address[7..0]
clock
q[31..0]
lpm_rom2
inst1
R
O
M
_A
D
[7
..
0]
rst
FLG
O_IR[7..0]
ROM[31..10]
ROM[7..0]
ROM[9..8]
clk
clk_1
ROM[31..0]
clk
7. Simulation
Addition
Here, a example is raised to test the function of the CPU.
Problem: Calculate the sum of all integers from 1 to 100.
Assuming in the memory:
sum is stored at location A4
temp is stored at location A3
the contents of location A0 is 0
the contents of location A1 is 1
the contents of location A2 is 64H
A0=20H.
A1=21H
A2=22H
A3=23H
Program Program with Instructions Contents of Memory(ram) in Hex
Address Contents
sum=0; LOAD A0 00 0020
STORE A4 01 0124
temp=100; LOAD A2 02 0022
STORE A3 03 0123
loop :sum=sum+temp; LOAD A4 04 0023
ADD A3 05 0223
STORE A4 06 0124
LOAD A3 07 0023
Microprogrammed CPU
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SUB A1 08 0321
STORE A3 09 0123
if temp>=0 goto loop JMPGEZ LOOP 0A 0A04
end HALT 0B 0C00
STORE A4 LOAD SUB STORE JMPGEZ LOAD ADD STORE
Overall addition result
Ending 6.372 ms
CLK 1us
Total cycle is 6372
Microprogrammed CPU
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Multiply
LOAD A0 00 0020(700)
MPY 01 0421(100)
HALT 02 0C00
According to the data in the figure, the final result is 216, which is recorded in MR, added
4464(shown in Signed dec), in ACC. So the result is 216 +4464=700*100=70000.
Division
LOAD A0 00 0020(10)
DIV 01 0D21(3)
HALT 02 0C00
In this case, 10/3, so the result is 3…1
Address0020=700
Multiply 0021(100)
Result in ALU(4464)
Result in MR(0001)
Initial data is 10 Recycling sub until flag is ‘1’
Result in DR is 3 and in ACC is 1
Microprogrammed CPU
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8. Conclusion and discussion
Conclusion
We can see the results of the simulation. The simulations of ADD, MPY and DIV are all
correct and correspondent to the requirement of the experiment. At the same time, all the functions
are well according to the principles.
The features of my design are basically threefold. First, the code of the design is precise and
concise as well. All the functions are included and the procedure is clear. Second, during the
codifying of the CPU, I strictly accord to the principle described in the task. Every part of the
entire structure is well-organized and well-connected. And the procedure is fluent, without any
contradiction. Third, I combine all the internal structure of CU to a chip”CU”. Although there is
not CAR or CBR, all the operations are included inside it, so the overall instruction could be more
convenient.
To be honest, the overall design of the CPU is really interesting and helped me to enhance my
ability of doing research and learning new skills. All the theories are clear after the classes; the
understanding of the design is further completed by referring to books rented from our library.
However, the utilization of the tools like Quartus is kind of missed and we need some more
reference to practical books. This helped me to concentrate myself on the procedure of the whole
experiment. I learned a lot.
Discussion
Although all the functions and procedures are strictly according to the principle, there are still lots
of promotion to be made. Such as the micro instructions could be simpler to reduce the burden of
CU. I can also use the concept of 2 ROM to further simplify the inner structure of CU, because the
first step of searching instruction can also be achieved in a smaller ROM.
In this case, I achieve the function of DIV in the micro-operations, I can also make it by codifying
certain loops in ALU, so the operations can be simpler.
Microprogrammed CPU
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9. Appendix
Micro-operations
Micro-operations Control memory
Current Address Jump Control
address Field Condition Signal
FETCH t1:MARPC 00 00 00 C8
CARCAR+1
t2:MBRRAM 01 00 00 C0,C9
PCPC+1
CARCAR+1
t3:IRMBR 02 00 00 C5
CARCAR+1
t4: CAROPMAP 03 OPMAP 10
LOAD t1:MARMBR 0A 00 00 C3
CARCAR+1
t2:MBRRAM 0B 00 00 C0
CARCAR+1
t3: BRMBR 0C 00 00 C6,C13
ACC0
CARCAR+1
t4: ALUBR+ACC 0D 00 00 C10,C11
CARCAR+1
OP=000
t5: ACCALU 0E 00 00 C12
CARCAR+1
t6: MARPC 0F 00 01 C8
CAR0
STORE t1:MARMBR 14 00 00 C3
CARCAR+1
t2:MBRACC 15 00 00 C2
CARCAR+1
t3: RAMMBR 16 00 00 C1
CARCAR+1
t4: MARPC 17 00 01 C8
CAR0
ADD x t1:MARMBR 1E 00 00 C3
CARCAR+1
t2:MBRRAM 1F 00 00 C0
CARCAR+1
t3: BRMBR 20 00 00 C6
CARCAR+1
t4: ALUBR+ACC 21 00 00 C10,C11
CARCAR+1
OP=000
Microprogrammed CPU
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t5: ACCALU 22 00 00 C12
CARCAR+1
t6: MARPC 23 00 01 C8
CAR0
SUB t1:MARMBR 28 00 00 C3
CARCAR+1
t2:MBRRAM 29 00 00 C0
CARCAR+1
t3: BRMBR 2A 00 00 C6
CARCAR+1
t4: ALUACC-BR 2B 00 00 C10,C11
CARCAR+1
OP=001
t5: ACCALU 2C 00 00 C12
CARCAR+1
t6: MARPC 2D 00 01 C8
CAR0
SHR t1: ALUACC 32 00 00 C11
CARCAR+1
t2: ACCALU 33 00 00 C12
CARCAR+1
OP=111
t3: MARPC 34 00 01 C8
CAR0
SHL t1: ALUACC 3C 00 00 C11
CARCAR+1
t2: ACCALU 3D 00 00 C12
CARCAR+1
OP=110
t3: MARPC 3E 00 01 C8
CAR0
AND x t1:MARMBR 46 00 00 C3
CARCAR+1
t2:MBRRAM 47 00 00 C0
CARCAR+1
t3: BRMBR 48 00 00 C6
CARCAR+1
t4: 49 00 00 C10,C11
ALUBR && ACC
OP=011
CARCAR+1
t5: ACCALU 4A 00 00 C12
CARCAR+1
t6: MARPC 4B 00 01 C8
CAR0
OR x t1:MARMBR 50 00 00 C3
CARCAR+1