电脑信号发出序列
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PE_RESET# must be asserted 100ms
after the power to the PCI-E
slots has been stabilized.
*SUS_CLK is delayed until PWRGD is
asserted while it acts as a
pinstrap. Once the first power up is
completed , SUS_CLK will a...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PE_RESET# must be asserted 100ms
after the power to the PCI-E
slots has been stabilized.
*SUS_CLK is delayed until PWRGD is
asserted while it acts as a
pinstrap. Once the first power up is
completed , SUS_CLK will always run
until PWRGD_SB is deasserted.
CPU_VLD
HT_VLD
ROMSTRAP
PE_RESET#
PWRGD_SB
MEM_VLD
PWRGD
HT_VLD----LPC_PWRDWN# : 0 ~12 ms
HT_VLD ----LPC_RESET# : 11 ~ 128 ms
CPU_PWROK
HT_STOP#
CPU_RST#
CPU - CK804
HT LINK
25MHz_xtal
+5V_DUAL
+3.3V_BAT
+3V_DUAL
SLP_S5#
+0.9V_VTT+1.8V_DUAL(ATX_PWRGD enable)
SLP_S3#
MAIN POWER
PCI_CLK/LPC_CLK
CPU_Vcore_EN
CLKOUT[2:0]_200MHz
CPU_Vcore
HTVDD_EN
+1.2V_HT
LPC_PWRDWN#
LPC_RESET#
PCI_RESET#[3:0]
A3
1 1Tuesday, October 10, 2006
Title
Size Document Number Rev
Date: Sheet of
5
5
4
4
3
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2
2
1
1
D D
C C
B B
A A
GPIO1 Bus GPIO1 only gates the assertion of the master CK804's PCI_RESET# in a multi-CK8-04 system
PCI_RESET#
HTVDD_EN
+1.2V_HT
HT_VLD
CPUVDD_EN
+V_CPU
CPU_VLD
CPU_CLK
LPC_CLK
SLP_S3#
MAIN POWER
PWRGD
+1.8V_SUS
+0.9V_VTT_SUS
SLP_S5#
MEM_VLD
Running
Running
RG/MII_TX_CLK
RG/MII_RX_CLK
PWRGD_SB
25Mhz xtal
BUF_25MHz
SUSCLK (32khz)
+5V_DUAL
+3.3V_DUAL
+1.2V_DUAL
+3.3V_VBAT
(ATX_PWRGD AND SLP_S3# AND MEM_PG)
(ATX_PWRGD)
(SLP_S5#)
A3
1 1Tuesday, October 10, 2006
Title
Size Document Number Rev
Date: Sheet of
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