SD卡Spec

SD Card Specification Simplified Version of: Part E1 Secure Digital Input/Output (SDIO) Card Specification Version 1.00 October 2001 SD Association Copyright 2000, 2001 SD Association SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 l Revision History Date Version Changes compared to previous issue October, 2001 1.0 Base version initial release Conditions for publication Publisher and Copyright Holder: SD Association 719 San Benito St. Suite C Hollister, CA 95023 USA Phone: +1 831 636 7322 Fax: +1 831 623 2248 E-mail: president@sdcard.org Confidentiality: This document is a simplified version of the original. This version is not required to be treated as confidential and Non Disclosure Agreement with neither the 3C LLC nor the SDA is required. Reproduction in whole or in part is prohibited without prior written permission of SDA. Exemption: None will be liable for any damages from use of this document. Important additional information! The reader is directed to the additional information available in section Error! Reference source not found.. This information will inform the reader of changes to the SDIO specification proposed for the next revision of this specification that should be considered in the design of any SDIO device. SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 i Table of Contents 1. General Description.......................................................................................................................................1 1.1 SDIO features.........................................................................................................................................1 1.2 Primary Reference Document................................................................................................................1 2. SDIO Signaling Definition..............................................................................................................................2 2.1 SDIO Card Types ...................................................................................................................................2 2.2 SDIO Card modes..................................................................................................................................2 2.2.1 SPI (Card mandatory support)........................................................................................................2 2.2.2 1-bit SD data transfer mode (Card mandatory support) .................................................................2 2.2.3 4-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed) ............2 2.3 SDIO Host Modes ..................................................................................................................................2 2.4 Signal Pins..............................................................................................................................................3 2.5 Host Requirements for SDIO .................................................................................................................3 3. SDIO Card Initialization .................................................................................................................................4 3.1 Differences in I/O card initialization........................................................................................................4 4. Differences with SD Memory Specification ...................................................................................................7 4.1 Unsupported SD Memory commands....................................................................................................7 4.2 Bus Width ...............................................................................................................................................8 4.3 Card Detect Resistor..............................................................................................................................8 4.4 Data Transfer Abort ................................................................................................................................8 4.5 Changes to SD Memory Fixed Registers...............................................................................................8 4.5.1 OCR Register..................................................................................................................................8 4.5.2 CID Register....................................................................................................................................8 4.5.3 RCA Register ..................................................................................................................................8 5. New I/O Read/Write Commands ...................................................................................................................9 5.1 IO_RW_DIRECT command (CMD52)....................................................................................................9 5.2 IO_RW_EXTENDED command (CMD53) .............................................................................................9 5.2.1 CMD53 Data Transfer Format.........................................................................................................9 6. SDIO Card Internal Operation .....................................................................................................................10 6.1 Overview...............................................................................................................................................10 6.2 Register Access Time...........................................................................................................................10 6.3 Interrupts ..............................................................................................................................................10 6.4 Suspend/Resume................................................................................................................................. 11 6.5 Read Wait (Optional)............................................................................................................................ 11 6.6 SDIO Fixed Internal Map......................................................................................................................12 6.7 Common I/O Area (CIA) .......................................................................................................................12 6.8 Card Common Control Registers (CCCR)...........................................................................................13 6.9 Function Basic Registers (FBR)...........................................................................................................13 6.10 Card Information Structure (CIS)......................................................................................................13 6.11 Multiple Function SD Cards..............................................................................................................13 6.12 Embedded I/O Code Storage Area (CSA)........................................................................................13 7. SDIO Interrupts............................................................................................................................................14 7.1 Interrupt Timing ....................................................................................................................................14 7.1.1 SPI and SD 1-bit mode interrupts .................................................................................................14 7.1.2 SD 4-bit mode ...............................................................................................................................14 7.1.3 Interrupt Clear Timing ...................................................................................................................14 8. SDIO Physical Properties............................................................................................................................15 8.1 SDIO Size.............................................................................................................................................15 8.2 SDIO Card Package.............................................................................................................................15 9. SDIO Mechanical Extensions......................................................................................................................16 9.1 Additional ESD/EMI Ground Point .......................................................................................................16 9.2 Extended Case.....................................................................................................................................16 9.3 Write Protect Switch .............................................................................................................................16 10. SDIO Power .............................................................................................................................................18 10.1 SDIO Card Initialization Voltage .......................................................................................................18 SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 ii 10.2 SDIO Power Consumption ...............................................................................................................18 10.3 SDIO Current ....................................................................................................................................18 11. Abbreviations and Terms .........................................................................................................................19 A.1 SD and SPI Command List........................................................................................................................A B.1 Normative References .............................................................................................................................. C C.1 Example SDIO Controller Design ............................................................................................................. D Table of Tables Table 1 SDIO pin definitions .................................................................................................................................3 Table 2 Unsupported SD Memory Commands.....................................................................................................7 Table 3 SDIO exceptions to SD physical section 8.1 requirements ...................................................................15 Table 4 SD Mode Command List..........................................................................................................................A Table 5 SPI Mode Command List .........................................................................................................................B Table of Figures Figure 1 Signal connection to two 4-bit SDIO cards ............................................................................................3 Figure 2 Card initialization flow in SD mode (SDIO aware host) .........................................................................5 Figure 3 Card initialization flow in SPI mode (SDIO aware host).........................................................................6 Figure 4 SDIO Internal Map................................................................................................................................12 Figure 5 SDIO Mechanical Extensions...............................................................................................................17 Figure 6 SDIO Internal State Machine example.................................................................................................. D Figure 7 State Diagram for Bus State Machine ................................................................................................... D Figure 8 State Diagram for Function State Machine.............................................................................................E SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 1 1. General Description The SDIO (Secure Digital I/O) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host will cause no physical damage or disruption of that device or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card will be via the normal means described in the SD specification with some extensions. In this state, the SDIO card will be idle and draw a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card will identify itself as an SDIO device. The host software will then obtain the card information in a tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to activate. This decision will be based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it will be allowed to power up fully and start the I/O function(s) built into it. 1.1 SDIO features � Targeted for portable and stationary applications � Minimal or no modification to SD Physical bus is required � Minimal change to memory driver software � Extended physical form factor available for specialized applications � Plug and play (PnP) support � Multi-function support including multiple I/O and combined I/O and memory � Up to 7 I/O functions plus one memory supported on one card. � Allows card to interrupt host � Initialization Voltage: 2.0 to 3.6V � Operational Voltage range: 3.1 to 3.5V 1.2 Primary Reference Document This spec is based on and refers extensively to the SDA document: SD Memory Card Specifications Part 1 PHYSICAL LAYER SPECIFICATION September 2000 Version 1.01 The reader is directed to this document for more information on the basic operation of SD devices. In addition, other documents are referenced in this specification. A complete list can be found in section B.1. SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 2 2. SDIO Signaling Definition 2.1 SDIO Card Types This specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full clock range of 0-25MHz. The Full-Speed SDIO devices have a data transfer rate of over 100 Mb/second (10 MB/Sec). A second version of the SDIO card is the Low-Speed SDIO card. This card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed SDIO cards shall support a full clock range of 0-400 KHz. The intended use of Low-Speed cards is to support low-speed IO devices with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a ‘Combo card’ (memory plus SDIO) then Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card. 2.2 SDIO Card modes There are 3 signaling modes defined for SD physical specification version 1.01 memory cards that also apply to SDIO Card: 2.2.1 SPI (Card mandatory support) The SPI bus topology is defined in section 3.1.2 and the protocol is defined in sections 3.2.2 and 7 of the SD Memory Card Specifications, PHYSICAL LAYER SPECIFICATION, Part 1,September 2000 Version 1.01. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification. 2.2.2 1-bit SD data transfer mode (Card mandatory support) This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in section 3.2.1 of the SD Memory Card specification. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification. 2.2.3 4-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed) This mode is identical to the 4 data bit mode (wide) defined for SD Memory in section 3.2.1 of the SD Memory Card specification. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is required, a special timing is required to provide interrupts. See section 7.1.2 for details of this operation. The 4-bit SD mode provides the highest data transfer possible, up to 100 Mb/sec. 2.3 SDIO Host Modes If a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes be supported. While a SDIO host that supports only the 4-bit transfer mode is possible, it’s performance with a Low-Speed SDIO card would be reduced. This is because the only means to transfer data to and from a Low-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command (CMD52) see 5.1). SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 3 2.4 Signal Pins Figure 1 Signal connection to two 4-bit SDIO cards Pin SD 4-bit mode SD 1-bit mode SPI mode 1 CD/DAT[3] Data line 3 N/C Not Used CS Card Select 2 CMD Command line CMD Command line DI Data input 3 VSS1 Ground VSS1 Ground VSS1 Ground 4 VDD Supply voltage VDD Supply voltage VDD Supply voltage 5 CLK Clock CLK Clock SCLK Clock 6 VSS2 Ground VSS2 Ground VSS2 Ground 7 DAT[0] Data line 0 DATA Data line DO Data output 8 DAT[1] Data line 1 or Interrupt (optional) IRQ Interrupt IRQ Interrupt 9 DAT[2] Data line 2 or Read Wait (optional) RW Read Wait (optional) NC Not Used Table 1 SDIO pin definitions It is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK to each slot, to allow the I/O devices to be placed in a low power state on a slot-by-slot basis. After reset, all data lines (DAT[3:0]) shall be in the hi-Z state on both the host and card(s) to avoid bus conflict. Access to the Bus Interface Control register within the CCCR determines DAT line mode. 2.5 Host Requirements for SDIO In order for a host to completely support all of the capabilities of the SDIO cards, some signal connections must be supported. In order to support interrupts, the host shall have Pin 8 connected from the card to the host in order to provide interrupt signaling. This is true even if the host will only support the SPI or 1 bit SD mode. In addition, if the host supports more than 1 card in either SD mode, the CMD and all 4 data lines (DAT[3:0]) should not be bussed togethe