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1. 秒模块程序清单 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity SECOND is port(clk,clr:in std_logic;----时钟/清零信号 sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位 co:out std_logic);-------输出/进位信号 end SECOND; architecture SEC of SECOND is begin process(clk,clr) variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数 begin if clr='1' then----当ckr为1时，高低位均为0 cnt1:="0000"; cnt0:="0000"; elsif clk'event and clk='1' then if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲） co<='1';----进位 cnt0:="1001";----低位为9 elsif cnt0<"1001" then----小于9时 cnt0:=cnt0+1;----计数 else cnt0:="0000"; if cnt1<"0101" then----高位小于5时 cnt1:=cnt1+1; else cnt1:="0000"; co<='0'; end if; end if; end if; sec1<=cnt1; sec0<=cnt0; end process; end SEC; 5.3分模块程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MINUTE is port(clk,en,clr:in std_logic; min1,min0:out std_logic_vector(3 downto 0); co:out std_logic); end MINUTE; architecture MIN of MINUTE is begin process(clk,en,clr) variable cnt1,cnt0:std_logic_vector(3 downto 0); begin if clr='1' then----当ckr为1时，高低位均为0 cnt1:="0000"; cnt0:="0000"; elsif clk'event and clk='1' then if en='1' then if cnt1="0101" and cnt0="1000" then co<='1'; cnt0:="1001"; elsif cnt0<"1001" then cnt0:=cnt0+1; else cnt0:="0000"; if cnt1<"0101" then cnt1:=cnt1+1; else cnt1:="0000"; co<='0'; end if; end if; end if; end if; min1<=cnt1; min0<=cnt0; end process; end MIN; 5.4时模块程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity HOUR is port(clk,en,clr:in std_logic; h1,h0:out std_logic_vector(3 downto 0)); end HOUR; architecture hour_arc of HOUR is begin process(clk) variable cnt1,cnt0:std_logic_vector(3 downto 0); begin if clr='1' then----当ckr为1时，高低位均为0 cnt1:="0000"; cnt0:="0000"; elsif clk'event and clk='1' then if en='1' then if cnt1="0010" and cnt0="0011" then cnt1:="0000"; cnt0:="0000"; elsif cnt0>="1001" then cnt1:=cnt1+1; cnt0:="0000"; else cnt0:=cnt0+1; end if; end if; end if; h1<=cnt1; h0<=cnt0; end process; end hour_arc; 扫描模块程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity SELTIME is port( clk:in std_logic; sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0); daout:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0)); end SELTIME; architecture fun of SELTIME is signal count:std_logic_vector(2 downto 0); begin sel<=count; process(clk) begin if(clk'event and clk='1') then if(count>="101") then count<="000"; else count<=count+1; end if; end if; case count is when"000"=>daout<= sec0; when"001"=>daout<= sec1; when"010"=>daout<= min0; when"011"=>daout<= min1; when"100"=>daout<=h0; when others =>daout<=h1; end case; end process; end fun; 5.6显示模块程序 library ieee; use ieee.std_logic_1164.all; entity DISPLAY is port(d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0)); end DISPLAY; architecture disp_are of DISPLAY is begin process(d) begin case d is when"0000" =>q<="0111111"; when"0001" =>q<="0000110"; when"0010" =>q<="1011011"; when"0011" =>q<="1001111"; when"0100" =>q<="1100110"; when"0101" =>q<="1101101"; when"0110" =>q<="1111101"; when"0111" =>q<="0100111"; when"1000" =>q<="1111111"; when others =>q<="1101111"; end case; end process; end disp_are;