Micro2440核心板原理图

1 2 3 4 5 6 A B C D 654321 D C B A CPU1 01-CPU1.Sch CPU2 02-CPU2.Sch CPU3 03-CPU3.Sch SDRAM 04-MEM.sch Micro2440核心板原理图 广州友善之臂计算机科技有限公司设计出品 www.arm9.net Schematic Diagram Designed by Guangzhou FriendlyARM 1 2 3 4 5 6 A B C D 654321 D C B A ADDR/GPA0F7 ADDR1E7 ADDR2B7 ADDR3F8 ADDR4C7 ADDR5D8 ADDR6E8 ADDR7D7 ADDR8G8 ADDR9B8 ADDR10A8 ADDR11C8 ADDR12B9 ADDR13H8 ADDR14E9 ADDR15C9 ADDR16D9 ADDR17G9 ADDR18F9 ADDR19H9 ADDR20D10 ADDR21C10 ADDR22H10 ADDR23E10 ADDR24C11 ADDR25G10 ADDR26D11 A I N 0 R 1 4 A I N 1 U 1 7 A I N 2 R 1 5 A I N 3 P 1 5 A I N 4 / T S Y M T 1 6 A I N 5 / T S Y P T 1 7 A I N 6 / T S X M R 1 6 A I N 7 / T S X P P 1 6 A r e f U 1 6 E X Y C L K H 1 2 C L K O U T 0 / G P H 9 R 9 C L K O U T 1 / G P H 1 0 P 1 0 M P L L C A P N 1 4 U P L L C A P P 1 7 O M 2 P 1 3 O M 3 T 1 3 X T I p l l G 1 4 X T O p l l G 1 5 X T I r t c M 1 4 X T O r t c L 1 2 T O U T 0 / G P B 0 J 6 T O U T 1 / G P B 1 J 5 T O U T 2 / G P B 2 J 7 T O U T 3 / G P B 3 K 3 T C L K 0 / G P B 4 K 4 T C L K 1 / E I N T 1 9 / G P G 1 1 U 1 2 DATA0 D12 DATA1 C12 DATA2 E11 DATA3 A13 DATA4 F10 DATA5 F11 DATA6 C13 DATA7 A14 DATA8 D13 DATA9 B15 DATA10 A17 DATA11 C14 DATA12 D15 DATA13 C15 DATA14 D14 DATA15 B17 DATA16 C16 DATA17 E15 DATA18 E14 DATA19 E13 DATA20 E12 DATA21 E16 DATA22 F15 DATA23 G13 DATA24 E17 DATA25 G12 DATA26 F14 DATA27 F12 DATA28 G11 DATA29 G16 DATA30 H13 DATA31 F13 n X D A C K 0 / G P B 9 L 3 n X D A C K 1 / G P B 7 K 7 n X D R E Q 0 / G P B 1 0 K 6 n X D R E Q 1 / G P B 8 K 5 n X B A C K / G P B 5 K 2 n X B R E Q / G P B 6 L 5 n G C S 0 F 6 n G C S 1 / G P A 1 2 B 2 n G C S 2 / G P A 1 3 C 3 n G C S 3 / G P A 1 4 C 4 n G C S 4 / G P A 1 5 D 3 n G C S 5 / G P A 1 6 C 2 n O E C 5 n W A I T E 4 n W E E 6 O M 0 T 1 5 O M 1 R 1 3 S3C2440 DMA Chip Select Address ADC Clock Timer Data U1A S3C2440X X T O r t c X T I r t c X T O p l l X T I p l l XTOpll XTIpll C6 15p C5 15p T S Y M C1 22p T S Y P C2 22p T S X M XTIrtc T S X P XTOrtc VDD33V LADDR0 LADDR1 LADDR2 LADDR3 LADDR4 LADDR5 LADDR6 LADDR7 LADDR8 LADDR9 LADDR10 LADDR11 LADDR12 LADDR13 LADDR14 LADDR15 LADDR16 LADDR17 LADDR18 LADDR19 LADDR24 LADDR25 n X D R E Q 0 n X D A C K 0 LDATA0 LDATA1 LDATA2 LDATA3 LDATA4 LDATA5 LDATA6 LDATA7 LDATA8 LDATA9 LDATA10 LDATA11 LDATA12 LDATA13 LDATA14 LDATA15 LDATA16 LDATA17 LDATA18 LDATA19 LDATA20 LDATA21 LDATA22 LDATA23 LDATA24 LDATA25 LDATA26 LDATA27 LDATA28 LDATA29 LDATA30 LDATA31 A I N 0 A I N 1 A I N 2 A I N 3 L 3 M O D E L 3 D A T A L 3 C L O C K X2 12M n L E D _ 1 n L E D _ 2 n L E D _ 3 n L E D _ 4 C L K O U T 0 C L K O U T 1 X1 32.768kHz n W A I T LADDR20 C40 2n7 C41 680p M P L L C A P MPLLCAP U P L L C A P UPLLCAP L n O E L n W E L n G C S 0 L n G C S 1 L n G C S 2 L n G C S 3 L n G C S 4 L n G C S 5 R68 4.7K E I N T 1 9 VDD33V G P B 0 G P B 1 R22 4.7K VDD33V OM0 LADDR21 LADDR22 1 2 J1 CON2 LADDR23 nRESET RST SW-PB 1 1 2 233 44 U9 MAX811 R2 470 VDD33V C34 104 M_nRESET 板载复位电路 1 2 3 4 5 6 A B C D 654321 D C B A nBE0:nWBE0:DQM0D4 nBE1:nWBE1:DQM1B5 nBE2:nWBE2:DQM2D5 nBE3:nWBE3:DQM3E5 nGCS6:nSCS0D2 nGCS7:nSCS1E3 nSCASD6 nSRASC6 SCKEA2 SCLK0B4 SCLK1B3 ALE/GPA18D1 CLE/GPA17F5 FRnBG6 NCONR12 nFCEGPA22F4 nFRE/GPA20E1 nFWE/GPA19F3 SDCLK/GPE5N8 SDCMD/GPE6K8 SDDATA0/GPE7R8 SDDATA1/GPE8M8 SDDATA2/GPE9P8 SDDATA3/GPE10J9 n C T S 0 / G P H 0 K 1 1 n R T S 0 / G P H 1 L 1 7 T X D 0 / G P H 2 K 1 3 R X D 0 / G P H 3 K 1 4 T X D 1 / G P H 4 K 1 6 R X D 1 / G P H 5 K 1 7 n R T S 1 / T X D 2 / G P H 6 J 1 1 n C T S 1 / R X D 2 / G P H 7 J 1 5 U C L K / G P H 8 K 1 5 n T R S T H 1 5 T C K J 1 3 T D I H 1 7 T D O J 1 6 T M S J 1 4 L E N D / G P C 0 L 1 V C L K / G P C 1 L 4 V L I N E : H S Y N C / G P C 2 M 1 V F R A M E : V S Y N C / G P C 3 L 7 V M : V D E N / G P C 4 M 4 L C D _ L P C O E / G P C 5 M 3 L C D _ L P C R E V / G P C 6 M 2 L C D _ L P C R E V B / G P C 7 P 1 L C D _ P W R E N / E I N T 1 2 / G P G 4 P 1 1 VD23/nSS0/GPD15 U5 VD22/nSS1/GPD14 N7 VD21/GPD13/USBRXD1 R6 VD20/GPD12/USBRXDN1 P6 VD19/GPD11/USBRXDP1 T5 VD18/GPD10/LPICLK1 R5 VD17/GPD9/SPIMOSI1 T4 VD16/GPD8/SPIMISO1 M7 VD15/GPD7/USBOEN1 N6 VD14/GPD6/USBTXDP1 P5 VD13/GPD5/USBTXDN1 R4 VD12/GPD4 P4 VD11/GPD3 R3 VD10/GPD2 N5 VD9/GPD1 M5 VD8/GPD0 R2 VD7/GPC15 P3 VD6/GPC14 M6 VD5/GPC13 P2 VD4/GPC12 N3 VD3/GPC11 R1 VD2/GPC10 N4 VD1/GPC9 L6 VD0/GPC8 N2 E I N T 2 3 / G P G 1 5 U 1 3 E I N T 2 2 / G P G 1 4 L 1 1 E I N T 2 1 / G P G 1 3 T 1 1 E I N T 2 0 / G P G 1 2 M 1 0 D P 1 / P D P 0 U 1 4 D N 1 / P D N 0 N 1 2 D P 0 N 1 1 D N 0 P 1 2 n S S 1 / E I N T 1 1 / G P G 3 R 1 0 n S S 0 / E I N T 1 0 / G P G 2 J 1 0 S P I C L K 1 / E I N T 1 5 / G P G 7 L 1 0 S P I C L K 0 / G P E 1 3 L 9 S P I M O S I 1 / E I N T 1 4 / G P G 6 R 1 1 S P I M O S I 0 / G P E 1 2 P 9 S P I M I S O 1 / E I N T 1 3 / G P G 5 K 1 0 S P I M I S O 0 / G P E 1 1 K 9 I 2 S S D O / I 2 S S D I / G P E 4 U 6 I 2 S S D I / n S S 0 / G P E 3 L 8 C D C L K / G P E 2 T 7 I 2 S S C L K / G P E 1 R 7 I 2 S L R C K / G P E 0 P 7 I I C S D A / G P E 1 5 M 9 I I C S C L / G P E 1 4 U 8 IIC IIS SPI USS TSP LCD DATA LCD CTRL JTAG UART SDIO NAND CTRL SDRAM U1B S3C2440X D N 0 D P 0 D N 1 D P 1 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 E I N T 2 0 L C D _ P W R V M V F R A M E V L I N E V C L K LED1 GREEN VDD33V LED2 GREEN LED3 GREEN LED4 GREEN nLED_1 nLED_2 nLED_4 nLED_3 SDCLK SDCMD SDDATA0 SDDATA1 SDDATA2 SDDATA3 LnSCAS LnSRAS LSCLK0 I 2 C S C L I 2 C S D A I 2 S L R C K I 2 S S C L K C D C L K I 2 S S D I I 2 S S D O G P G 1 3 G P G 1 4 G P G 1 5 S P I M I S O S P I M O S I S P I C L K n S S _ S P I W P _ S D n C T S 0 n R T S 0 T X D 0 R X D 0 T X D 1 R X D 1 T X D 2 R X D 2 n T R S T T C K T D I T D O T M S ALE CLE RnB NCON nFCE nFRE nFWE NR8 1K NR5 1K NCON GPG13 GPG14 GPG15 VDD33V E I N T 1 3 E I N T 1 4 E I N T 1 5 E I N T 1 1 L E N D R401K R411K R421K R431K NR1 10K NR2 10K NR3 10K NR4 10K LLnSCS0 LLnSCAS LLnSCAS LLnSRAS LLnSRAS LLSCKE LLSCLK0 LLSCLK0 LLSCLK1 LnWBE0 LnWBE1 LnWBE2 LnWBE3 LLSCKE LSCKE LSCLK1LLSCLK1 LnSCS0LLnSCS0 R36 22 R54 22 R55 22 R63 22 R65 22 R66 22 L C D V F 0 L C D V F 1 L C D V F 2 G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O G P I O _ I O 1 2 3 4 5 6 7 8 9 10 JTAG2 HEADER 4X2 VDD33V R61 10K R60 10K R59 10K R58 10K R57 1KnTRST TDI TMS TCK nRESET TDO 板载JTAG接口 1 2 3 4 5 6 A B C D 654321 D C B A nRESETH16 nRSTOUT/GPA21N13 EINT0/GPF0N17 EINT1/GPF1M16 EINT2/GPF2L13 EINT3/GPF3M15 EINT4/GPF4M17 EINT5/GPF5L14 EINT6/GPF6L15 EINT7/GPF7L16 EINT8/GPG0N9 EINT9/GPG1T9 EINT16/GPG8T10 EINT17/GPG9/nRST1M11 EINT18/GPG10/nCTS1N10 CAMPCLK/GPJ8G5 CAMVSYNC/GPJ9G7 CAMHREF/GPJ10G2 CAMCLKOUT/GPJ11J3 CAMRESET/GPJ12J4 CAMDATA0/GPJ0H6 CAMDATA1/GPJ1G3 CAMDATA2/GPJ2H5 CAMDATA3/GPJ3H4 CAMDATA4/GPJ4H3 CAMDATA5/GPJ5H7 CAMDATA6/GPJ6J8 CAMDATA7/GPJ7H2 V S S i a r m H 1 v s s i a r m K 1 V S S i a r m T 1 V S S i a r m T 2 V S S i a r m U 4 V S S i a r m U 7 V S S i a r m U 1 0 V S S M O P B 1 V S S M O P E 2 V S S M O P D 1 7 V S S M O P D 1 6 V S S M O P A 1 5 V S S M O P B 1 3 V S S M O P A 1 1 V S S M O P A 7 V S S M O P A 5 V S S M O P N 1 V S S M O P U 3 V S S M O P U 9 V S S M O P U 1 5 V S S M O P G 1 V S S M O P H 1 1 VSSA_UPLL M12 VSSA_mPLL R17 VSSi G17 VSSi C17 VSSi A12 VSSi B10 VSSi A4 VSSi A3 VSSi F2 VSSA_ADC T14 VDDMOP(SCLK,100MHz:3.3V) C1 VDDMOP(SCLK,100MHz:3.3V) F17 VDDMOP(SCLK,100MHz:3.3V) B16 VDDMOP(SCLK,100MHz:3.3V) B14 VDDMOP(SCLK,100MHz:3.3V) B12 VDDMOP(SCLK,100MHz:3.3V) A9 VDDMOP(SCLK,100MHz:3.3V) B6 V D D i a r m ( 1 . 2 V ) J 2 V D D i a r m ( 1 . 2 V ) L 2 V D D i a r m ( 1 . 2 V ) U 1 V D D i a r m ( 1 . 2 V ) U 2 V D D i a r m ( 1 . 2 V ) T 6 V D D i a r m ( 1 . 2 V ) U 1 1 V D D A _ U P L L ( 1 . 2 V ) M 1 3 V D D A _ M P L L ( 1 . 2 V ) N 1 6 V D D i ( 1 . 2 V ) A 1 V D D i ( 1 . 2 V ) A 6 V D D i ( 1 . 2 V ) A 1 0 V D D i ( 1 . 2 V ) B 1 1 V D D i ( 1 . 2 V ) A 1 6 V D D i ( 1 . 2 V ) F 1 6 V D D i ( 1 . 2 V ) F 1 V D D a l i v e ( 1 . 2 V ) G 4 V D D a l i v e ( 1 . 2 V ) J 1 7 V D D _ a d c ( 3 . 3 V ) P 1 4 V D D _ R T C ( 3 . 3 V ) N 1 5 P W R E N J 1 2 n B A T T _ F L T H 1 4 EXT INT CAMERA IF VDDOP()3.3V) J1 VDDOP()3.3V) T3 VDDOP()3.3V) T12 VDDOP()3.3V) K12 V D D i a r m ( 1 . 2 V ) T 8 U1C S3C2440X P W R E N VDD33V VDD33V EINT16 EINT17 EINT18 EINT9 CAM_PCLK CAM_VSYNC CAM_HREF CAMCLK CAMRST CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA7 nRESET VDD1.25VVDD1.25V EINT0 EINT1 EINT2 EINT3 C14 100nF C15 100nF C16 100nF C17 100nF C18 100nF C19 100nF VDD33V C20 100nF C21 100nF C22 100nF C23 100nF C24 100nF C25 100nF VDD1.25V R10 15K VDD33V EINT4 EINT5 1 TP1 CON1 EINT6 EINT7 EINT8 CA1 100nF CA2 100nF CA3 100nF CA4 100nF CA5 100nF CA6 100nF CA7 100nF CA8 100nF CA9 100nF CA10 100nF CA11 100nF CA12 100nF CA13 100nF CA14 100nF CA15 100nF CA16 100nF CA17 100nF CA18 100nF CA19 100nF CA20 100nF CA21 100nF CA22 100nF CA23 100nF V D D R T C C9 10uF C12 10uF C3 100nF C7 100nF VDD5V Vin1 G N D 2 Vout 3 NC 4 U4 LM1117-33 OUT 1IN2 G N D 3 OUT 4 SET 5CC6 /SHDN7 /FAULT 8 U3 MAX8860EUA18 C39 100nF C13 33nF/6.3V R33 10(1%) R32 100K(1%) C4 10uF/10V VDD33V R31 0 C11 10uF/10V VDD1.25V VDD33V Power RED R1 330 VDD33V 电源电路 3.3V产生电路 1.25V产生电路 1 2 3 4 5 6 A B C D 654321 D C B A A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 A1135 BA121 nWE 16 nSRAS 18 nSCS 19 nSCAS 17 LDQM15 UDQM39 SCKE37 SCLK38 VDD2 27 VDD1 14 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDDQ0 3 VSS254 VSS141 VSS028 VSSQ352 VSSQ246 VSSQ112 VSSQ06 BA020 VDD0 1 VDDQ3 49 VDDQ2 43 VDDQ1 9 A1236 U7 HY57V561620FTP-H A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 A1135 BA121 nWE 16 nSRAS 18 nSCS 19 nSCAS 17 LDQM15 UDQM39 SCKE37 SCLK38 VDD2 27 VDD1 14 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDDQ0 3 VSS254 VSS141 VSS028 VSSQ352 VSSQ246 VSSQ112 VSSQ06 BA020 VDD0 1 VDDQ3 49 VDDQ2 43 VDDQ1 9 A1236 U6 HY57V561620FTP-H VDD33V VDD33V LnWBE0 LnWBE1 LSCKE LSCLK0 LnSCS0 LnSRAS LnSCAS LnWE LnWBE2 LnWBE3 LSCKE LSCLK1 LnSCS0 LnSRAS LnSCAS LnWE LADDR2 LADDR3 LADDR4 LADDR5 LADDR6 LADDR7 LADDR8 LADDR9 LADDR10 LADDR11 LADDR12 LADDR13 LADDR14 LADDR24 LADDR25 LADDR2 LADDR3 LADDR4 LADDR5 LADDR6 LADDR7 LADDR8 LADDR9 LADDR10 LADDR11 LADDR12 LADDR13 LADDR14 LADDR24 LADDR25 LDATA0 LDATA1 LDATA2 LDATA3 LDATA4 LDATA5 LDATA6 LDATA7 LDATA8 LDATA9 LDATA10 LDATA11 LDATA12 LDATA13 LDATA14 LDATA15 LDATA16 LDATA17 LDATA18 LDATA19 LDATA20 LDATA21 LDATA22 LDATA23 LDATA24 LDATA25 LDATA26 LDATA27 LDATA28 LDATA29 LDATA30 LDATA31 VDD33V CLE16 ALE17 WE18 WP 19 I/O0 29 I/O1 30 I/O2 31 I/O3 32 VSS13 VCC 12 I/O4 41 I/O5 42 I/O6 43 I/O7 44 VCC 37 R/B7 RE8 CE9 VSS36 SE6 U2 K9Fxx08 LDATA0 LDATA1 LDATA2 LDATA3 LDATA4 LDATA5 LDATA6 LDATA7 nFWE nFRE ALE nFCE CLE RnB C10 0.1uF R6 10K VDD33V C30 100nF C31 100nF C32 100nF C33 100nF VDD33V C26 100nF C27 100nF C28 100nF C29 100nF VDD33V A025 A124 A223 A322 A421 A520 A619 A718 A88 A97 A106 A115 A124 A133 A142 A151 A1648 A1717 A1816 A199 A20/NC10 A21/NC13 D0 29 D1 31 D2 33 D3 35 D4 38 D5 40 D6 42 D7 44 D8 30 D9 32 D10 34 D11 36 D12 39 D13 41 D14 43 D15 45 VDD 37 OE 28 WE 11 CE 26 /RST/NC 12 /WP 14 NC15 NC47 VSS27 VSS46 U10 AM29LV160DB/SST39VF1601 LDATA15 LDATA14 LDATA13 LDATA12 LDATA11 LDATA10 LDATA9 LDATA8 LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 LADDR20 LADDR19 LADDR18 LADDR17 LADDR16 LADDR15 LADDR14 LADDR13 LADDR12 LADDR11 LADDR10 LADDR9 LADDR8 LADDR7 LADDR6 LADDR5 LADDR4 LADDR3 LADDR2 LADDR1 nRESET LnGCS0 LnWE VDD33V LnOE VDD33V LADDR21 LADDR22 R3 10K R4 10K VDD33V nXDREQ0 nXDACK0 EINT6 EINT5 nRESET LADDR11 GPB1GPB0 LADDR10 EINT18 LADDR9 EINT17 EINT4 LADDR8 EINT3 EINT1 LADDR7 LADDR6 LADDR5 LADDR4 LADDR3 LADDR2 GNDVDD5V LADDR1 LADDR0 EINT11 EINT15 nWAIT EINT14 EINT13 LnWE LnOE LnWBE1 LnGCS4 LnGCS2 LnGCS1 EINT7 LDATA15 LDATA14 LDATA13 LDATA12 LDATA11 LDATA10 LDATA9 LDATA8 LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 GND LADDR24 LADDR20 LADDR19 LADDR18 LADDR17 LADDR16 LADDR15 LADDR14 LADDR13 LADDR12 LnGCS3 EINT9 VDD5V I2CSCLI2CSDA AIN0 AIN1 AIN2 VDDRTC WP_SD nCTS0 nRTS0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 EINT16 EINT0 EINT2 L3MODE L3DATA L3CLOCK I2SLRCK I2SSCLK CDCLK I2SSDI I2SSDO SDCLK SDCMD SDDATA0 SDDATA1 SDDATA2 SDDATA3 LADDR21LADDR22 LADDR23 EINT19 DN0 DN1 DP0 DP1 EINT8 LCDVF0 M_nRESET OM0 VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 CAM_PCLK CAM_VSYNCCAM_HREF CAMCLK CAMRST CAMDATA0 CAMDATA1 CAMDATA2 CAMDATA3 CAMDATA4 CAMDATA5 CAMDATA6 CAMDATA7 VDD5VGND LCD_PWRVM VFRAMEVLINE VCLKLEND TSYMTSYP TSXMTSXP EINT20 核心板引脚图 Micro2440V2 对任何一排引脚的的5V和GND上电均可对核心板进行jtag烧录编程 核心板封装见Protel99SE文件 PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 PA33 PA35 PA37 PA39 PA41 PA43 PA45 PA47 PA49 PA51 PA53 PA55 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 PA32 PA34 PA36 PA38 PA40 PA42 PA44 PA46 PA48 PA50 PA52 PA54 PA56 MICRO2440A MICRO2440 PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 PB33 PB35 PB37 PB39 PB41 PB43 PB45 PB47 PB49 PB2 PB4 PB6 PB8 PB10 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 PB32 PB34 PB36 PB38 PB40 PB42 PB44 PB46 PB48 PB50 MICRO2440B MICRO2440 PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 PC17 PC19 PC21 PC23 PC25 PC27 PC29 PC31 PC33 PC35 PC37 PC39 PC41 PC43 PC45 PC47 PC49 PC51 PC53 PC55 PC2 PC4 PC6 PC8 PC10 PC12 PC14 PC16 PC18 PC20 PC22 PC24 PC26 PC28 PC30 PC32 PC34 PC36 PC38 PC40 PC42 PC44 PC46 PC48 PC50 PC52 PC54 PC56 MICRO2440C MICRO2440