SD储存卡资料手册

mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 1 Description Transcend High Capacity microSD Card series are specifically designed to meet the High Capacity, High Definition Audio and Video requirement for the latest Digital Cameras, DV Recorders, Mobile Phones, etc. The new defined Speed Class enables the host to support AV applications to perform real time recording to the microSD memory card. Placement Front Back Features • RoHS compliant product. • Operating Voltage: 2.7 ~ 3.6V • Operating Temperature: -25 ~ 85°C • Durability: 10,000 insertion/removal cycles • Compatible with SD Specification Ver. 2.0 • Comply with SD File System Specification Ver. 2.0 • Mechanical Write Protection Switch with microSD adapter • Supports Speed Class Specification Class 6 • Supports Copy Protection for Recorded Media (CPRM) for SD-Audio 1 2 3 4 5 6 7 8 • Seamless compatibility with SDMI-compliant digital audio devices • Form Factor: 11mm x 15mm x 1mm Pin Definition SD Mode SPI Mode Pin No. Name Type Description Name Type Description 1 DAT2 I/O/PP Data Line [Bit2] RSV Reserved 2 CD/DAT3 I/O/PP Card Detect / Data Line [Bit3] CS I Chip Select 3 CMD PP Command / Response DI I Data In 4 VDD S Supply voltage VDD S Supply voltage 5 CLK I Clock SCLK I Clock 6 VSS S Supply voltage ground VSS S Supply voltage ground 7 DAT0 I/O/PP Data Line [Bit0] DO O/PP Data out 8 DAT1 I/O/PP Data Line [Bit1] RSV Reserved S: Power Supply; I:Input; O:Output; PP:Push-Pull mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 2 Architecture mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 3 Bus Operating Conditions • General Parameter Symbol Min. Max. Unit Remark Peak voltage on all lines -0.3 VDD+0.3 V All Inputs Input Leakage Current -10 10 µA All Outputs Output Leakage Current -10 10 µA • Power Supply Voltage Parameter Symbol Min. Max. Unit Remark Supply voltage VDD 2.7 3.6 V Output High Voltage VOH 0.75* VDD V IOH=-100uA@VDD Min. Output Low Voltage VOL 0.125* VDD V IOL=100uA@VDD Min. Input High Voltage VIH 0.625* VDD VDD+0.3 V Input Low Voltage VIL VSS-0.3 0.25* VDD V Power up time 250 ms From 0v to VDD Min. • Current Consumption The current consumption is measured by averaging over 1 second. ‧ Before first command: Maximum 15 mA ‧ During initialization: Maximum 100 mA ‧ Operation in Default Mode: Maximum 100 mA ‧ Operation in High Speed Mode: Maximum 200 mA ‧ Operation with other functions: Maximum 500 mA. • Bus Signal Line Load The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance C USB C itself and the capacitance CCARD of each card connected to this line: L = CHOST + CBUS + Ν*CCARD Where N is the number of connected cards. Parameter Symbol Min. Max. Unit Remark Pull-up resistance RCMD RDAT 10 100 kΩ To prevent bus floating Bus signal line capacitance CL 40 pF 1 card CHOST+CBUS shall not exceed 30 pF mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 4 Single card capacitance CCARD 10 pF Maximum signal line inductance 16 nH fPP ≤ 20 MHz Pull-up resistance inside card (pin1) RDAT3 10 90 kΩ May be used for card detection Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD Memory Card host. Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than maximum value of CL (40 pF). mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 5 • Bus Signal Levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range: Parameter Symbol Min. Max. Unit Remark Output HIGH voltage VOH 0.75* VDD V IOH = -100 μA @VDD min Output LOW voltage VOL 0.125* VDD V IOL = -100 μA @VDD min Input HIGH voltage VIH 0.625* VDD VDD + 0.3 V Input LOW voltage VIL VSS – 0.3 0.25* VDD V mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 6 • Bus Timing Parameter Symbol Min Max. Unit Remark Clock CLK (All values are referred to min (VIH) and max (VIL) Clock frequency Data Transfer Mode fPP 0 25 MHz CCARD ≤ 10 pF, (1 card) Clock frequency Identification Mode fOD 0(1)/100 400 KHz CCARD ≤ 10 pF, (1 card) Clock low time tWL 10 ns CCARD ≤ 10 pF, (1 card) Clock high time tWH 10 ns CCARD ≤ 10 pF, (1 card) Clock rise time tTLH 10 ns CCARD ≤ 10 pF, (1 card) Clock fall time tTHL 10 ns CCARD ≤ 10 pF, (1 card) Inputs CMD, DAT (referenced to CLK) Input set-up time tISU 5 ns CCARD ≤ 10 pF, (1 card) Input hold time tIH 5 ns CCARD ≤ 10 pF, (1 card) Outputs CMD, DAT (referenced to CLK) mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 7 Output Delay time during Data Transfer Mode tODLY 0 14 ns CL ≤ 40 pF, (1 card) Output Delay time during Identification Mode tODLY 0 50 ns CL ≤ 40 pF, (1 card) (1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 8 • Bus Timing (High Speed Mode) Parameter Symbol Min Max. Unit Remark Clock CLK (All values are referred to min (VIH) and max (VIL) Clock frequency Data Transfer Mode fPP 0 50 MHz CCARD ≤ 10 pF, (1 card) Clock low time tWL 7 ns CCARD ≤ 10 pF, (1 card) Clock high time tWH 7 ns CCARD ≤ 10 pF, (1 card) Clock rise time tTLH 3 ns CCARD ≤ 10 pF, (1 card) Clock fall time tTHL 3 ns CCARD ≤ 10 pF, (1 card) Inputs CMD, DAT (referenced to CLK) Input set-up time tISU 6 ns CCARD ≤ 10 pF, (1 card) Input hold time tIH 2 ns CCARD ≤ 10 pF, (1 card) Outputs CMD, DAT (referenced to CLK) mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 9 Output Delay time during Data Transfer Mode tODLY 14 ns CL ≤ 40 pF, (1 card) Output Hold time tOH 2.5 ns CL ≤ 40 pF, (1 card) Total System capacitance for each line1 CL 40 pF (1 card) 1) In order to satisfy severe timing, host shall drive only one card. mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 10 Reliability and Durability Temperature Operation: -25°C / 85°C Storage: -40°C (168h) / 85°C (500h) Junction temperature: max. 95°C Moisture and corrosion Operation: 25°C / 95% rel. humidity Storage: 40°C / 93% rel. hum./500h Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009 Durability 10.000 mating cycles; test procedure: tbd. Bending 10N Torque 0.15N.m or +/-2.5 deg Drop test 1.5m free fall UV light exposure UV: 254nm, 15Ws/cm² according to ISO 7816-1 X-ray exposure 0.1 Gy of medium-energy radiation (70 keV to 140 keV, cumulative dose per year) to both sides of the card, according to ISO7816-1. Visual inspection Shape and form No warp page; no mold skin; complete form; no cavities surface smoothness <= -0.1 mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.) Minimum moving force of WP witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector.) WP Switch cycles minimum 1000 Cycles(@Slide force 0.4N to 5N) mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 11 Register Information Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands (see Chapter 4.7). The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters. 1. OCR register The 32-bit operation conditions register stores the VDD voltage profile of the card. Additionally, this register includes status information bits. One status bit is set if the card power up procedure has been finished. This register includes another status bit indicating the card capacity status after set power up status bit. The OCR register shall be implemented by the cards. The 32-bit operation conditions register stores the VDD voltage profile of the card. Bit 7 of OCR is newly defined for Dual Voltage Card and set to 0 in default. If a Dual Voltage Card does not receive CMD8, OCR bit 7 in the response indicates 0, and the Dual Voltage Card which received CMD8, sets this bit to 1. Additionally, this register includes 2 more status information bits. Bit 31 - Card power up status bit, this status bit is set if the card power up procedure has been finished. Bit 30 - Card capacity status bit, this status bit is set to 1 if card is High Capacity SD Memory Card. 0 indicates that the card is Standard Capacity SD Memory Card. The Card Capacity status bit is valid after the card power up procedure is completed and the card power up status bit is set to 1. The Host shall read this status bit to identify a Standard or High Capacity SD Memory Card. The OCR register shall be implemented by the cards. OCR Register Definition mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 12 1) This bit is valid only when the card power up status bit is set. 2) This bit is set to LOW if the card has not finished the power up routine. The supported voltage range is coded as shown in Table 5-1. A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW. 2. CID Register The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following paragraphs: • MID An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register. • OID A 2-character ASCII string that identifies the card OEM and/or the card contents (when used as a llocated distribution media either on ROM or FLASH cards). The OID number is controlled, defined, and a rer by the SD-3C, LLC. This procedure is established to ensure to a SD Memory Card manufactu niqueness of the CID register. u Note: SD-3C, LLC licenses companies that wish to manufacture and/or sell SD Memory Cards, including but not limited to flash memory, ROM, OTP, RAM, and SDIO Combo Cards. SD-3C, LLC is a limited liability company established by Matsushita Electric Industrial Co. Ltd., SanDisk Corporation and Toshiba orporation. C • PNM he product name is a string, 5 ASCII characters long. T PRV • mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 13 The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an “n.m” ble. s an example, the PRV binary value field for product revision “6.2” will be: 0110 0010 PSN e Serial Number is 32 bits of binary number. MDT al digits, one is 8 bit representing the year(y) e binary value of the Date field for production date “April 2001” will be: 1 0100. bits). SD Version 1.0. The Cell Type field is coded as follows: R = readable, W(1) = itable once, W = multiple writable. revision number. The “n” is the most significant nibble and “m” is the least significant nib A • Th • The manufacturing date composed of two hexadecim and the other is four bits representing the month(m). The “m” field [11:8] is the month code. 1 = January. The “y” field [19:12] is the year code. 0 = 2000. As an example, th 0000000 • CRC CRC7 checksum (7 3. CSD Register Table 5-16 shows Definition of the CSD for the High Capacity SD Memory Card (CSD Version 2.0). The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card. CSD Version 2.0 is applied to only the High Capacity SD Memory Card. The field name in parenthesis is set to fixed value and indicates that the host is not necessary to refer these fields. The fixed values enables host, which refers to these fields, to keep compatibility to C wr mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 14 The CSD Register Fields (CSD Version 2.0) The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first. • CSD_STRUCTURE Field structures of the CSD register are different depend on the Physical Specification Version and Card Capacity. The CSD_STRUCTURE field in the CSD register indicates its structure version. The following table shows the version number of the related CSD structure. mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 15 CSD Register Structure • TAAC This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations (See 4.6.2). • NSAC This field is fixed to 00h. NSAC should not be used to calculate time-out values. • TRAN_SPEED The following table defines the maximum data transfer rate per one data line - TRAN_SPEED: mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 16 Note that for current SD Memory Cards that field must be always 0_0110_010b (032h) which is equal to 25MHz - the mandatory maximum operating frequency of SD Memory Card. In High-Speed mode, that field must be always 0_1011_010b (05Ah) which is equal to 50MHz. And when the timing mode returns to the default by CMD6 or CMD0 command, its value will be 032h. • CCC The SD Memory Card command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. A value of ‘1’ in a CCC bit means that the corresponding command class is supported. • READ_BL_LEN This field is fixed to 9h, which indicates READ_BL_LEN=512 Byte. • READ_BL_PARTIAL This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed. • WRITE_BLK_MISALIGN This field is fixed to 0, which indicates write access crossing physical block boundaries is always disabled in High apacity SD Memory Card. C • READ_BLK_MISALIGN This field is fixed to 0, which indicates read a disabled in High Capacity SD Memory Card. ccess crossing physical block boundaries is always • DSR_IMP Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR)must be implemented also. mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 17 • C_SIZE This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum memory space specified by a 32-bit block address.) This parameter is used to calculate the user data area capacity in the SD memory card (not include the protected area). The user data area capacity is calculated from C_SIZE as follows: memory capacity = (C_SIZE+1) * 512K byte As the maximum capacity of the Physical Layer Specification Version 2.00 is 32 GB, the upper 6 bits of this field shall be set to 0. • ERASE_BLK_EN This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes. • SECTOR_SIZE This field is fixed to 7Fh, which indicates 64 KBytes. This value does not relate to erase operation. Version 2.00 cards indicates memory boundary by AU size and this field should not be used. • WP_GRP_SIZE This field is fixed to 00h. The High Capacity SD Memory Card does not support write protected groups. • WP_GRP_ENABLE This field is fixed to 0. The High Capacity SD Memory Card does not support write protected groups. • R2W_FACTOR This field is fixed to 2h, which indicates 4 multiples. Write timeout can be calculated by multiplying the read access time nd R2W_FACTOR. However, the host should not use this factor and should use 250 ms for write timeout a WRITE_BL_LEN • This field is fixed to 9h, which indicates WRITE_BL_LEN=512 Byte. WRITE_BL_PARTIAL • his field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed. T FILE_FORMAT_GRP • mmmiiicccrrroooSSSDDDHHHCCC CCCaaarrrddd ssseeerrriiieeesss High Capacity microSD Card Transcend Information Inc. 18 This field is set to 0. Host should not use this field. COPY onsumers, is set to ‘1’ which identifies the card contents as a copy. The COPY bit is an one time programmable bit. PERM_WRITE_PROTECT erase commands for this card re permanently disabled). The default value is ‘0’, i.e. not permanently write protected. for this rd are temporarily disabled). This bit can be set and reset. The default value is ‘0’, i.e. not write protected. is field is set to 0. Host should not use this field. sum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD ntents. d the command classes. A ‘+’ entry indicates at the CSD field affects th • Defines if the contents is original (= ‘0’) or has been copied (=’1’). The COPY bit for OTP and MTPdevices, sold to end c • Permanently protects the whole card content against overwriting or erasing (all write and a • TMP_WRITE_PROTECT Temporarily protects the whole card content from being overwritten or erased (all write and erase commands ca • FILE_FORMAT Th • CRC The CRC field carries the check sum for the CSD contents. The check co The following table lists the correspondence between the CSD entri