主板检测卡

主板检测卡 Motherboard test card Computer motherboard inspection card (also known as motherboard inspection card) is used Master board diagnostics (check) card: another POST card or Debug card He is to use the current accord with ATX BTX structure, and other similar structure or compatible X86 structure of the standard of a computer is program execution and by detecting circuit testing to see if there is damage Computer starts, under this standard signal is triggered by the switch, the COMS chip front-end circuit is initialized, using 5 VSB power to maintain, and test for a normal, 5 VSB and MOS controller connected to the + 5 VSB line signal switch power supply circuit, PWM control, initialize disk 12 v circuit, initialize disk 5 v circuit, initializes the memory power, initialize the processor power, into the PCI bus power supply (if there is a PCI - E is to start the first PCI - E, followed by AGP and then the PCI and ISA) after complete power-up COMS in accordance with the rules, submit self-check chip control, respectively to test the all board equipment, due to the PCI, AGP ISA PCI - E bus are all the signal circuit, the signal circuit is not only for their own initialization circuit, also as a feedback loop, so the mainboard test card can use this circuit signal to determine most of the working condition of the equipment And through the other foot of the PCI slot, check the computer for all the careful state, including the display card and bus state, disk state, processor, memory, and so on Anyway, that's how it works These signals are all pulse dc signal, they caught carrying a certain information, through the test card after decoding, display on the screen, or by light shows that power supply with indicator light display directly If you can't pass the test and report it, then you can find out what part of the problem is through his manual But only for reference, test card is not a perfect thing, he will often appear error state, so can not only have his results as the final judgment. Watch must read: There are three cases of special code "00" and "ff" and other starting codes: It has been followed by a series of other code, "00" or "ff", and the motherboard is ok. If there is no error in the cmos setup, a non-serious failure will not affect the continuation of the BIOS self check, and the end result will be "00" or "ff". The "00" or "ff" or "ff" or any other starting code is turned on and the main board is not running. This table is sorted by code value from small to large, and the card is in an uncertain order. Not listed in the undefined code table. 4, for different BIOS (common ami, award, phoenix) with the same code on behalf of the meaning of different, so should make clear what you detect computer belongs to which a type of BIOS, you can refer to your computer using manual, or directly from the motherboard BIOS chip view, also can see directly in the startup screen. The pci slot with a few mainboards appears only in part of the code, but the isa slot has a complete self-checkout code output. And has found a rare original installed motherboard isa slots without code output, while the pci slot with complete code output, therefore, it is recommended that you check the code is not successful, will this double slot card to another slot to try. Different pci slot in addition, the same motherboards, some slot have send the complete code, such as dell810 only close to the CPU mainboard, according to a pci slot have complete code has been change to "00" or "ff", while other pci slot go after "38" does not continue to change. The time required for the reset signal is not necessarily in sync with the pci, so it is possible that isa is starting to code, but the pci reposition light is not out, so pci code stops to start the code. Code synopsis The configuration of the system is displayed; You will control the INI19 boot load. 01 processor test 1, processor status verification, if test fails, The second channel timer is tested in half; The 8254 channel 2 timer is about to complete the test. The first 64DK RAM was the fifth fault. Establish the interrupt vector table used for 8259. The second channel timer test is over; The 8254 first channel timer is about to complete the test. The first 64DK RAM no. 6 failed. Set the video input/output job, and the video BIOS is enabled. The first channel timer test is over; The 8254 0line timer is about to complete the test. The first 64DK RAM was the seventh failure. Test the video memory, if the installation of the video BIOS is passed by, it can be bypassed. The 0th channel timer test is over; The memory is being updated soon. The first 64DK RAM was the eighth failure. Test the interrupt controller (8259) for the first channel. The memory is now being updated and the memory is updated. The first 64DK RAM was the ninth failure. 1A test the interrupt controller (8259) of channel 2. The memory update line is being triggered to check for 15 microseconds/breaks. The first 64DK RAM was the 10th fault. 1B test CMOS battery level. Complete memory update time 30 microsecond tests; The basic 64K memory test is about to begin. The first 64DK RAM was the 11th failure. 1C test CMOS total. The first 64DK RAM was the 12th failure. 1D sets the CMOS configuration. The first 64DK RAM no. 13 failed. 1E determines the size of the system memory and compares it to the CMOS value. The first 64DK RAM was the 14th failure. 1F test 64K memory to the highest 640K. The first 64DK RAM was the 15th failure. Measure fixed 8259 interrupt bit. Start the basic 64K memory test; Will test the address line. Dependent DMA register tests are ongoing or failing. Maintain an unblocking interrupt (NMI) bit (check for parity or input/output channels). Through the address line test; It's about to trigger parity. The primary DMA register test is ongoing or failing. Test the interrupt function of 8259. End trigger parity; The serial data read/write test will begin. The main interrupt mask registers test is being performed or failed. Test protection mode 8086 virtual mode and 8086 page mode. Basic 64K serial data read/write tests are normal; Any adjustment before the interrupt vector initialization is about to begin. The dependent interrupt mask memory test is being performed or failed. Measuring more than 1MB of extended memory. Any adjustment prior to the initialization of the vector will begin the initial preparation of the interrupt vector. Set the ES segment address register to the memory high end. Test all memory after the first 64K. Complete the initial preparation of the interrupt vector; The input/output port of 8042 will be read for rotary interrupter. The load interrupt vector is being performed or failed. Exceptions to the method of test protection. Read 8042 input/output ports; It is about to start preparing the global data for a rotational interruption. Open the A20 address line; Let the entry in. To determine the control or block RAM of the super-fast buffer memory. All 1 data is initially ready for completion; Then any initial preparation after the interrupt vector is performed. Keyboard controller tests are ongoing or malfunction. Determine the control of super-fast buffer memory or special 8042 keyboard controller. The initial preparation after completing the interrupt vector; The color scheme is about to be adjusted. CMOS power failure/check summation is ongoing. The color scheme of the ordered color will be adjusted. A review of the effectiveness of the CMOS configuration is ongoing. 2A makes the keyboard controller initial preparation. Color mode has been adjusted to trigger parity before the ROM test. Empty 64K base memory. Make the disk drive and the controller initial preparation. Trigger parity; You will control any adjustments required before the optional video ROM. Screen memory tests are ongoing or failing. 2C check the serial port and prepare the original. Finish before the video ROM control; Check out the optional video ROM and control it. Screen initial preparation is ongoing or malfunction. 2D detects parallel ports and makes the work initial ready. Completed optional video ROM control, which will be controlled by any other processing after the video ROM restore control. Screen rescan tests are ongoing or fail. 2E makes hard disk drives and controllers initial preparation. Processing recovery from video ROM control; If no EGA/VGA is found to be on display memory read/write tests. Testing the video ROM is ongoing. 2F tests the math coprocessor and prepares the work. Didn't find EGA/VGA; Will start the display memory read/write test. . Establish basic memory and extend memory. Read/write tests on display memory. A scan is pending. Think that screens work. Test the selection of ROM from C800:0 to EFFF: 0, and make the work initial. The display memory reads/writes tests or scans fail, and another display memory reads/writes tests. Monochrome monitors can work. The I/O chip programming for the COM/LTP/FDD/sound device on the motherboard is suitable for setting values. Read/write tests on another monitor; Another display scan will be performed. The color monitor (40 columns) can work. 333. The video monitor is over. Will begin to use the adjustment switch and the actual card to check the type of display. Color monitors (80 columns) can work. The display adapter has been inspected; Then the display mode is set. The timer ticks off the test and the test is in or out. Complete the set up display mode; The data area for the BIOS ROM will be examined. The outage test is on or off. The BIOS ROM data area has been checked; The cursor that is about to adjust the information. A - 20 failed in the door circuit. 337. The cursor that identifies the information is completed; The message is about to be displayed. Unexpected interruptions in the protection mode. Complete the display of the electrical information; Read the new cursor position. The RAM test is running or the address failure. Read the save cursor position and display the reference information string. . 3A. Information is about to be displayed. Interval timer channel 2 test or malfunction. 3B USES the OPTI circuit (only 486) to make the auxiliary supercache memory initial preparation. Already shown < ESC > information; Virtual mode, the memory test is about to start. Daily calendar clock tests are ongoing or malfunction. 3C establishes the mark that allows access to CMOS Settings. Serial port tests are ongoing or failing. 3D initialization keyboard/PS2 mouse/PNP device and total memory node. Parallel port tests are ongoing or failing. 3E tries to open the L2 cache. The math coprocessor test is being performed or failed. Start preparing for virtual tests; It's going to be tested from the video memory. Adjust the CPU speed to match the peripheral clock. 41 interruption was open and initializes the data's 0-0 draw in order to facilitate the examination transform (interrupt controller or bad memory) inspection after recovery from video memory; Prepare the descriptor table. System plugin board selection failed. 42 displays the window into SETUP. The descriptor table is ready; Virtual methods are about to be tested in memory. Extend the CMOS RAM failure. 43 if plug and play BIOS, The serial port and the gate are initialized. Enter the virtual mode; An interrupt is about to be implemented for diagnostics. The interrupt is implemented (for example, the diagnostic switch is switched on; the data is about to be initialized to check the memory in 0:0.) The BIOS interrupt is initialized. 45 initializes the math coprocessor. The data is initially prepared; The memory is going to be checked at 0:0 and the size of the system memory. . The test memory is returned; The memory size is computed and the page is written to test the memory. Check the read-only memory ROM version. The upcoming memory trial page; The base 640K memory will be written to the page. The basic memory is written to the page; The memory that is about to be determined over 1MB. Video check, CMOS reconfiguration. Identify and verify the memory of 1BM. The memory that is about to be determined over 1MB. . 4A. Find more than 1MB of memory and check it. Will check the BIOS ROM data area. You initialize the video. 4B. The examination of the BIOS ROM data area is over, and will check < ESC > and the memory for the soft reset of 1MB. A memory (soft reset) that clears more than 1MB of memory. Blocks the video BIOS ROM. 4 d. A memory that has been cleared over 1MB (soft reset); Will save the size of the memory. . 4E if there is a mistake; Display the error message on the display and wait for the customer to press the < F1 > key to continue. Test of memory: (no soft reset); A test that will show the first 64K memory. Display copyright information. 4F read and write soft, hard disk data, DOS boot. Start showing the size of the memory and are testing the memory to update it; Serial and random memory tests will be performed. . The CMOS value of the current BIOS is stored in the CMOS. Complete memory testing under 1MB; The size of the upcoming cache to be redefined and masked. Send the CPU type and speed to the screen. Test more than 1MB of memory. . All the ISA read-only memory ROM is initialized, and the initialization of the IRQ is eventually assigned to the PCI. More than 1MB of memory testing; Ready to go back to the real address. Enter keyboard detection. If the BIOS is not plug and play, the value of the serial port, parallel port, and Settings is initialized. Save the size of the CPU register and memory, and will enter the real address. . Successfully start the real address; The register that will be saved when the recovery is ready for downtime. Scanning "hit key" The register has been restored and will disable the address line of the door circuit a-20. . Successfully disable the a-20 address line; Will check the BIOS ROM data area. The keyboard test is over. The BIOS ROM data area is half checked; To continue. . The data section of the BIOS ROM is completed; Will clear the < ESC > information. No interrupt testing is set. Has cleared the < ESC > information; Information is displayed; The tests for DMA and interrupt controllers are about to begin. . 5A.. displays the Settings under the "F2" key. 5B.. test the base memory address. 5C.. Test 640K base memory. Set up the hard disk to boot the fan area virus protection function. Testing through DMA page registers; The video memory will be tested. Test the extended memory. Displays the system configuration table. The video memory test is over; Testing of the DMA# 1 base register is pending. . Start system boot with interrupt 19H. Testing through the DMA# 1 base register; A test for DMA# 2 registers is pending. Test the extended memory address line. Pass the DMA# 2 basic register test; Will check the BIOS ROM data area. . 64. The completion of any initial preparation required after the optional ROM test; The base address of the data area or printer that will set up the timer. . 9A. The return operation after setting the timer and the basic address of the printer; The rs-232 base address is set. Shielding ROM options. 9B. Return after the rs-232 base address. The initial preparation for the coprocessor test is imminent. . 9C. The initial preparation required for the completion of the coprocessor test; The coprocessor is then initialized. Establish power saving management. 9d.the coprocessor is ready for any initial preparation after the coprocessor test. . 9E. The initial preparation after completing the coprocessor will check the extended keyboard, keyboard identifier, and number lock. Open hardware interrupts. 9F. Has been checked to extend the keyboard, to set up the identification mark, the number lock to be switched on or off, the keyboard identification command will be issued. . A0. The keyboard identification sign is about to be restored. Set the time and date. The keyboard identification sign is restored; Then the cache memory is tested. . The speed buffer memory test is over. Any soft errors will be displayed. Check keyboard lock. A3. The speed at which the keyboard will be hit. . The speed of the keyboard, the waiting state of the memory. The keyboard repeats the input rate initialization. A5. The screen is then cleared. . A6. The screen is cleared. The parity and unmasking interrupts are about to start. . A7. Enabled unmasked interrupts and parity; Any initial preparation required to control the optional ROM at E000:0. . A8. Control ROM is ready to end before E000:0, followed by any initial preparation required after controlling the E000:0. Clear the "F2" key prompt. A9. From the control of the E000:0 ROM, you will be ready for any initial preparation required after controlling the E000:0 optional ROM. . AA. The initial preparation after controlling the optional ROM. The configuration of the system will be displayed. Scan the "F2" button. Enter Settings. Uncheck the electrical self-check mark. B0.. check for non-critical errors. Prepare to enter the operating system boot. B4.. the buzzer rings. B6. Check the password Settings (optional). B8.. Clear the full description table. The BC.. clears the checkcheck value. The BE program defaults to the control chip, which corresponds to the modulated binary default table. Clear the screen (optional). BF tests CMOS for establishing values. Check the virus for a data backup. The C0 initializes the cache. Use interrupt 19 to try the boot. C1 memory self-checking. Find the "55" and "AA" tags in the boot sector. The C3 first 256K memory test. .. C5 copies the BIOS from ROM for quick self-examination. .. The C6 cache self-check. .. The CA detects the Micronies overspeed buffer memory (if it exists) and makes it initial. .. CC shut off the non-blocking interrupt handler. .. An unexpected exception to the EE processor. .. FF gives INI19 boot loader control, the mainboard OK. Different motherboard detecting card code is different! The usual code that appears to be unsolved by this code is: 75 C1 C0 EF The explanation is as follows: 75: scan the hardware configuration, check the hard disk, the optical drive device and the relevant interface equipment and the connection to have no trouble C1 or C0: memory failure EF: the BIOS failure, you need to discharge the cmos If a boot check card has a voltage display and no code is displayed, check the CPU for failure Indicator lamp description: The BIOS lamp is running the lamp for the BIOS, and it should keep flashing when working properly The CLK lamp is a clock light, normally bright The OSC lamp is the base clock lamp, normally bright The RRSET lamp is a resetting lamp, which will flash when normal restart, then put out the curtain RUN lights should be kept flashing for running lights + 12V, -12v, + 5V, + 3.3 V lights are normal