主板诊断卡代码说明

主板诊断卡代码说明 The motherboard diagnostic card code shows the computer diagnostic card 50, 2007, the 14th of 2009 Diagnostic card is to use the motherboard BIOS internal self-check program in the test results, in hexadecimal character code signal, so as to judge the state of the computer through the code or failure (such as black screen). Computer, the BIOS will test computer mainboard circuit, memory, peripherals, hard disk, floppy disk and keyboard, and analysis/initialization initialization, after all is well, is to guide the operating system. Diagnostic card expansion slot inserted in host may have built-in (part), and then depending on the type of the BIOS (different BIOS AMI, Award, Phoenix, for example, even if unified code meaning may be different, if your motherboard manual or computer use manual instructions, you should This should be based on the fact that the hexadecimal code predicted on the diagnostic card is the fault. Need of special note is, diagnostic card code sequence is not necessary but is since the childhood, was turned on "00" or "FF" or other began code and stabilization for plate is not running, and has a series of other code again after "00", or "FF ", the main board OK. The code Award BIOS Ami BIOS Phoenix BIOS or Tandy 3000 BIOS The configuration of the system is predicted; The next moderation INI19 guide is loaded. . 1 processor test 1, processor status verification, and if the test fails, the cycle is infinite. The test of the processor register is about to start, and no blocking interrupts will be stopped. The CPU register test is ongoing or failing. Determine the type of diagnosis (normal or manufacturing). If the keyboard detente contains a number, it will be invalid. No blocking interrupts; By delaying the starting point. CMOS write/read is in or out. The 48042 keyboard regulator, the TESTKBRD command (AAH), has been completed. ROM BIOS checking device is on or off. Reposition the 8042 keyboard and verify the TESTKBRD. Keyboard moderator soft reset/electrical test. Programmable interval timer tests are being performed or failed. If you repeatedly make test 1 through 5, you will get 8042 moderation. Confirm the soft reset/power; The boot ROM. The DMA is in or out of order. Make circuit film initial preparation, disable video, odd-even, DMA circuit, and broken root DMA circuit, all page register and CMOS stop byte. The ROM ROM BIOS check sum is already started and the check for the keyboard to ease the conflict is broken. The DMA initialization page The face register reads/writes tests are being performed or failed. Processor test 2, verify the CPU register. ROM BIOS check sum is normal, the keyboard detente the conflict device has broken root, the BAT (the basic envelope test) commands to the keyboard. . Make the CMOS timer as the initial preparation, normal update timer cycle. The BAT command has been sent to the keyboard and will be written to the BAT command. The RAM update test is ongoing or failing. The 2009 EPROM check sum must be equal to zero. Verify the basic package test for the keyboard, then verify the keyboard command bytes. The first 64K RAM test is underway. 0A makes the video interface an initial preparation. The keyboard command byte code, which is about to be written to the command byte value. The first 64K RAM chip or numeric line failure, shift. 0B test 8254 channel 0. Write the keyboard moderator command byte, which is about to make the blocking/unlock command of the pins 23 and 24. The first 64K RAM chi/even logic failed. 0C test 8254 channel 1. The keyboard moderator pins 23, 24 has been blocked/unlocked. The NOP command has been issued. The address line of the error was 64K RAN. 0D 1, check that CPU speed is compatible with the system. Second, check that the control chip has been programmed to match the initial setting. The video channel test, if failed, honking. Processing the NOP command; Then the CMOS stop the register. Higher-value 64 k The parity of RAM fails 0E to test CMOS outage bytes. CMOS stop open register to read/write tests; The CMOS check sum is calculated. Initialize the input/output port address. 0F test expanded CMOS. Computed CMOS review total writing diagnostic bytes; CMOS starts with a start. . Test DMA channel 0. CMOS has been initially planned and the CMOS status register will be initially scheduled for date and time. The first 64K RAM zero fault. Test DMA channel 1. The CMOS status register has been set up to disable DMA and interrupt moderators. The error of the first 64DK RAM was a fault. Test the DMA page register. Stop the DMA control 1 and interrupt moderation 1 and 2; The video predictor is pending and the port B is initially planned. The first 64DK RAM was the second failure. Test 8741 keyboard moderator interface. The video predictor has been discontinued, port B has been initially planned; Initial circuit wafer initialization/memory detection. The first 64DK RAM was a third failure. The test memory update is triggered by the triggered circuit. The circuit chip initializer/memory is automatically checked out; The 8254 timer test is about to start. The first 64DK RAM was a fourth failure. Test the beginning of 64K system memory. The second channel timer tests half the wall; The 8254 channel 2 timer is about to complete the test. The first 64DK RAM was the fifth fault. Establish the interrupt vector table used for 8259. The second channel timer test is over; The 8254 first channel timer is about to complete the test. The first 64DK RAM was the sixth failure. Set the video input/output thing, if the video BIOS is installed. The first channel timer test is over; The 8254 0line timer is about to complete the test. The first 64DK RAM was the seventh failure. Test the video memory, if the installation of the video BIOS is passed by, it can be bypassed. The 0th channel timer test is over; Upcoming update memory. The first 64DK RAM was the eighth failure. Test the interrupt moderator of channel 1 (8259). The memory is updated and the memory is updated. The first 64DK RAM was the ninth failure. 1A test the interruption moderator (8259) barrier in channel 2. The memory update line is being triggered to check for 15 microseconds/breaks. The first 64DK RAM was the 10th fault. 1B test CMOS battery level. Complete memory update time 30 microsecond tests; The starting basic 64K memory test. The first 64DK RAM was the 11th failure. 1C test CMOS total. The first 64DK RAM was the 12th failure. 1D sets the CMOS configuration. The first 64DK RAM was the 13th failure. 1E the size of the system memory, and the ratio of the CMOS value to the CMOS. The first 64DK RAM was the 14th failure. 1F test 64K memory to the highest 640K. The first 64DK RAM was the 15th failure. Measure fixed 8259 interrupt bit. Starting basic 64K memory test; Will test the address line. Dependent DMA register tests are ongoing or failing. No blocking interrupt (NMI) (parity or input/output channel checks). Through the address line test; It's about to be triggered by the odd sex. The primary DMA register test is ongoing or failing. Test the interruption of 8259. The end of the touch is triggered by parity; Read/write the first serial numeric reads/write tests. The main interrupt mask registers test is being performed or failed. Test protection mode 8086 virtual mode and 8086 page mode. Basic 64K serial numeric reads/writes tests are normal; Any adjustment before the initial discontinuity vector is initialized. The dependent interrupt mask memory test is being performed or failed. Set up more than 1MB of extended memory. Any adjustment prior to the initialization of the vector will be the initial preparation of the initiating interrupt vector. Set the ES segment address register to the memory high end. Test all memory after the first 64K. Complete the initial preparation of the interrupt vector; The input/output port of 8042 will be read for the rotary interrupter. The load interrupt vector is being performed or failed. The case of test protection. Read 8042 input/output ports; The global numerical value is set to be initially planned for the start of rotary interrupter. Open the A20 address line; Let the entry in. Identify the moderating or blocking RAM of the ultra-high speed mitigating conflict memory. All 1 numerical initial preparation is completed; Then any initial preparation after the interrupt vector is performed. The keyboard moderator test is on or off. Determine the temperance of the ultra high speed detente conflict memory or the special 8042 keyboard regulator. The initial preparation after completing the interrupt vector; The color scheme is about to be adjusted. CMOS power failure/check summation is ongoing. The color scheme of the ordered color will be adjusted. CMOS configuration useful checks are ongoing. 2A enables the keyboard moderator to do initial preparation. Color mode has been fixed, and the pre-rom test has been triggered to trigger parity. Empty 64K base memory. Make the disk drive and the moderator initial preparation. It's triggered the odd sex ending; Any adjustments needed before the video ROM will be selected for moderation. Screen memory tests are ongoing or failing. 2C check the serial port and make the work initially planned. Finish before the video ROM control; Check out the optional video ROM and moderation. The screen initial preparation is ongoing or failing. 2D detects parallel ports and enables the work to be initially planned. Complete the optional video ROM moderation, which will be followed by any other treatment after the video ROM restore moderation. Screen rescan tests are ongoing or fail. 2E makes the hard computer drive and the moderator initial preparation. Recovery from the treatment of the video ROM; If no EGA/VGA was invented, the prepredictor memory read/write test was performed. Testing the video ROM is ongoing. 2F tests the math coprocessor and makes the work initial. No invention EGA/VGA; To be read/write tests on the beginning of the header. . Establish basic memory and extend memory. Read/write tests in a predictor's memory; Electronic scanning will be on the way. It's ok to think of a screen. Test the selection of ROM from C800:0 to EFFF: 0, and make the work initially planned. A failure to read/write tests or an electronic scan in a predictor's memory is about to undergo another type of predictor memory read/write test. A monochrome monitor is something that can be done. To set the value for the I/O chip programming on the main board, COM/LTP/FDD/sound gear. Read/write tests in a different predictor. Another predictive electronic scan will be performed. The color monitor (40 columns) can be done. The video indicates the end of the inspection. Use the adjustment switch and the actuator to check the closing type of the indicator. Color monitors (80 columns) are ok. Testing the indicator adapter; Then set the prediction method. The timer ticks off the test and the test is in or out. Complete the setting of the forecast; The numerical area for the BIOS ROM is to be examined. The outage test is on or off. The BIOS ROM value area has been checked; The cursor that is about to adjust the information. A - 20 failed in the door circuit. 337. The cursor that identifies the information is completed; The news is about to be predicted. Unexpected interruptions in the protection mode. Complete the prediction of the electrical information; Read the new cursor position. The RAM test is running or an address failure. Reading the saved cursor position is about to indicate the reference information string. . 3A. The information is about to be invented. Interval timer channel 2 test or malfunction. 3B USES the OPTI circuit (only 486) to assist in the initial preparation of the assisted super-fast conflict memory. The ESC > information has been heralded. Virtual mode, memory test is about to start. Daily calendar clock tests are ongoing or malfunction. 3C establishes the mark that allows access to CMOS Settings. Serial port tests are ongoing or failing. 3D initialization keyboard/PS2 mouse/PNP equipment and total memory nodes. Parallel port tests are ongoing or failing. 3E tries to open the L2 cache. The math coprocessor test is being performed or failed. A test of the virtual style of the first name; It's going to be tested from the video memory. Adjust CPU speed to match the peripheral clock. 41 interruption was open and initializes the value's 0-0 draw in order to facilitate the examination transform (interrupt control device or memory bad) reply from video memory test after the Renaissance; To prepare the descriptor table. System plugin board selection failed. 42 indicates the window enters SETUP. The description table has been set up; Virtual methods are about to be tested in memory. Extend the CMOS RAM failure. If the BIOS is plug and play, the serial port and the port are initialized. Enter the virtual mode; It is about to be interrupted by the fact that the diagnosis is made. . Has made the fact interrupt (for example, the diagnostic switch is on); the number is to be initially planned to check the memory in 0:0. The BIOS interrupt is initialized. 45 initializes the math coprocessor. The numerical value has been set up for initial preparation; The memory is going to be checked at 0:0 and the size of the system memory. . The test memory is returned; The memory size calculation is finished, and the page will be written to test the memory. Check the read-only memory ROM version. The upcoming memory trial page; The base 640K memory will be written to the page. . The basic memory is written to the page; The memory that is about to be determined over 1MB. Video check, CMOS reconfiguration. Identify and verify the memory of 1BM. The memory that is about to be determined over 1MB. . 4A. Find more than 1MB of memory and check it. Will check the BIOS ROM values area. You initialize the video. The 4B. BIOS ROM area test is over, and will check < ESC > and the memory for the soft reset over 1MB. . 4c. the memory (soft reset) of more than 1MB is about to be broken by more than 1MB of memory. . 4D has more than 1MB of memory (soft reset). Will save the size of the memory. . 4E if there is a mistake; Presage error message on the predictor and wait for the customer to press the < F1 > key to continue. Test starting memory: (no soft reset); A test that is about to predict the performance of the upcoming 64K memory. Predictive copyright information. 4F read and write soft, hard disk value, do DOS instruction. The starting point indicates the size of the memory and is testing the memory to be updated; Serial and random memory tests will be performed. . The CMOS value of the current BIOS is stored in the CMOS. Complete memory testing under 1MB; The size of the upcoming cache to be redefined and masked. Send the CPU type and speed to the screen. 51. Test the memory of more than 1MB. . All ISA read-only memory ROM is initialized, and the final issue of initialization such as IRQ is assigned to the PCI. More than 1MB of memory testing; It is about to get back to the real site. Enter keyboard detection. If the BIOS is not plug and play, the value of the serial port, parallel port, and Settings is initialized. Save the size of the CPU register and memory, and will enter the real address. . Successfully start the real address; The register that will be saved when the recovery is planned. Electron scanning "impact key" The register has been restored and will disable the address line of the door circuit a-20. . Successfully disable the a-20 address line; Will check the BIOS ROM values area. The keyboard test is over. The BIOS ROM values section is checked for half the wall; To continue. . The numerical section of the BIOS ROM is completed; Invention of the broken root < ESC > information. No interrupt testing is set. The broken root < ESC > information; Information has been predicted; Testing of the upcoming DMA and interrupt moderators. . 5A... The "F2" key is predicted to be set. 5B.. test the base memory address. 5C.. Test 640K base memory. Set up the hard drive to guide the protection of virus protection. Testing through DMA page registers; The video memory will be tested. Test the extended memory. 61 indicates the system configuration table. The video memory test is over; Testing of the DMA# 1 base register is pending. . The starting head USES the interrupt 19H for systematic guidance. Testing through the DMA# 1 base register; A test for DMA# 2 registers is pending. Test the extended memory address line. Pass the DMA# 2 basic register test; Will check the BIOS ROM values area. . The BIOS ROM values section is checked for half the wall and continues. . The BIOS ROM numerical area check is over; The DMA devices 1 and 2 will be programmed. . The DMA device 1 and 2 are programmed to end; The initial preparations are to be made using the 59 interrupter. The Cache registry is optimized for configuration. The initial preparations have been completed; Upcoming keyboard test. . Make external Cache and CPU internal Cache events. 6A.. test and predict external Cache values. 6C... Foreshadows the intrinsic meaning of being blocked. 6E.. Indicates the dependent configuration information. The detected error code is sent to the screen. The test configuration is incorrect. Test not the clock. Scanning keyboard errors. 7A.. lock the keyboard. 7C.. Set the hardware interrupt vector. 7E.. Test the installation of a math processor. The keyboard test starts, is breaking root and check to have the key stuck, will make the keyboard return to revival. Closed programmable input/output equipment. Find the key to the wrong keyboard for recovery. A test command to set up the keyboard sparingly. . The keyboard moderator interface test is over, and will be written to the command byte and to make the cycle detente the conflict device initial preparation. Check and install the fixed RS232 interface (serial port). Having written to the command byte, the initial preparation of the global value has been completed; You are going to check for a key lock. . Check that the lock key is checked to check if the memory is missing from the CMOS. Check and install the fixed parallel port. The memory size; Will predict soft errors and password or bypassing. . Checking the password; The program is about to be pre-arranged. Re-open the programmable I/O equipment and detect if there is a conflict between fixed I/O. Complete the pre-set programming; Programming for CMOS setup. . Recover the broken root screen from the CMOS decoration program; You're going to be programming later. Initialize the BIOS value area. Complete the programming after the decoration; You will be able to predict the information on the screen. . 8A. Indicates the first screen information. Expand the BIOS numeric area initialization. 8B. Predicted information: the first and video BIOS will be blocked. . 8C. Successfully block the first and video BIOS and program the post-cmos setup. Initialize the floppy drive. 8D. Has been programmed for optional items, then checks the mouse and the initial preparation. . 8E. Test the mouse and complete the initial preparation; The hard and floppy disk will be reset. . 8F. The floppy disk has been checked, the disk will be initially planned and then the floppy disk will be fitted. . Code Award BIOS Ami BIOS Phoenix BIOS or Tandy 3000 BIOS The floppy disk configuration is over; You will test the presence of the hard disk. The hard disk moderator is initialized. The hard disk has been tested; The hard disk is then configured. Local bus hard disk moderator initialization. The hard disk configuration is complete; The numerical area for the BIOS ROM is to be examined. Jump to user path 2. The numerical area of the BIOS ROM is checked for half the wall; To continue. . The numerical area of the BIOS ROM is completed, which is the size of the basic and extended memory. Close the a-20 address line. Adjust the size of the memory in response to the mouse and the hard disk type 47 support; Will be tested for memory. . The test indicates the recovery of recovery after memory; Upcoming C800:0 optional ROM before the initial preparation. The "ES section" registry is broken. C800: any initial preparation that was preceded by the optional ROM, followed by the check and moderation of the optional ROM. . The abstinence of the optional ROM. Any processing that will be required after the optional ROM is returned to moderation. Search ROM options. The completion of any initial preparation required after the optional ROM test; The base address of the numerical area or printer that will set up the timer. . 9A. The return operation after setting the timer and the basic address of the printer; The rs-232 base address is set. Shielding ROM options. 9B. Return after the rs-232 base address. The initial preparations for the coprocessor test will be performed. . 9C. The coprocessor is then initialized. Establish power saving management. 9D. The coprocessor is ready for initial preparation and will be ready for any initial preparation after the coprocessor test. . 9E. After completing the coprocessor's initial preparation, the extension keyboard, keyboard identifier, and number lock will be checked. Open hardware interrupts. 9F. Has been checked to extend the keyboard, to set up the identification mark, the number lock to be switched on or off, the clapping keyboard to recognize the command. . A0. The keyboard recognition symbol will be restored. Set the time and date. The keyboard recognition sign reviled; Then the high-speed detente conflict memory test. . The high speed mitigating conflict memory test is over; It is about to predict any soft errors. Check keyboard lock. A3. A soft error indicates the end; The speed at which the keyboard impact is set. . The impact rate of the keyboard is adjusted to prepare the waiting status of the memory. The keyboard is initialized with repeated input rates. A5. Memory waits for the end; And then you have the broken root screen. . A6. The screen is broken; The parity and unmasking interrupts are about to start. . A7. Unblocked interrupts and parity are enabled; The ROM that is about to be moderated in order to be able to choose from the E000: any initial preparation that is required for the E000:0. . A8. The moderation ROM is completed before the initial preparation of E000:0, followed by any initial preparation required after the E000:0. Break root "F2" key hint. A9. From the control of E000:0 ROM, the E000 is about to be in moderation: any initial preparation required after the optional ROM. . AA. The configuration of the system is imminent. Electronic scanning "F2" key shocks. Enter Settings. AE. B0.. check for non-critical errors. B2. The operation system guidance is completed by the self-examination. B4.. the buzzer rings. B6. Detect the dark code Settings (optional). B8. The broken root describes the table. BC.. The check value of the broken root. The BE program defaults to the moderated chip, which corresponds to the modulated binary default table. Break the root screen (optional). BF tests CMOS for establishing values. Check the virus for a data backup. The C0 initializes the cache. Use the interrupt 19 test guide. C1 memory self-checking. Look for the "55" and "AA" tags in the sector. C3: the first 256K memory test. .. C5 copies the BIOS from ROM for quick self-examination. .. The C6 cache self-check. .. The CA detects the Micronies overspeed conflict memory (if it exists) and enables the work to be initially planned. .. CC shut off no blocking interrupt handler. .. An unexpected exception to the EE processor. .. Computer haven't started the E0 This may be a CPU not installed May also be a motherboard is out of question You can check the CPU are put away Put the motherboard battery power FF gives INI19 guidance to the moderation of the program, the mainboard OK