Modern Semiconductor Devices for Integrated CircuitsChenming-Hu-ch3-slides

nullnullModern Semiconductor Devices for Integrated Circuits (C. Hu)Slide 3-*Chapter 3 Device Fabrication TechnologyAbout 1020 transistors (or 10 billion for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale Integration) GSI (Giga-Scale Integration)Variations of this versatile technology are used for flat-panel displays, micro-electro-mechanical systems (MEMS), and chips for DNA screening... nullSlide 3-*3.1 Introduction to Device FabricationOxidationLithography & Etching Ion ImplantationAnnealing & DiffusionModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.2 Oxidation of SiliconModern Semiconductor Devices for Integrated Circuits (C. Hu)3.2 Oxidation of SiliconSlide 3-*3.2 Oxidation of SiliconSi + O2  SiO2 Si +2H2O  SiO2 + 2H2Dry Oxidation : Wet Oxidation : Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*EXAMPLE : Two-step Oxidation (a) How long does it take to grow 0.1m of dry oxide at 1000 oC ? (b) After step (a), how long will it take to grow an additional 0.2m of oxide at 900 oC in a wet ambient ? Solution: (a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to grow 0.1m of oxide. (b) Use the “900oC wet” curve only. It would have taken 0.7hr to grow the 0.1 m oxide and 2.4hr to grow 0.3 m oxide from bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.3.2 Oxidation of SiliconModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.3 LithographyModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.3 LithographyPhotolithography Resolution Limit, R R ³ kl due to optical diffraction Wavelength l needs to be minimized. (248 nm, 193 nm, 157 nm?) k (<1) can be reduced will Large aperture, high quality lens Small exposure field, step-and-repeat using “stepper” Optical proximity correction Phase-shift mask, etc. Lithography is difficult and expensive. There can be 40 lithography steps in an IC process.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.3 LithographyWafers are being loaded into a stepper in a clean room.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*conventional dry lithographywet or immersion lithography3.3.1 Wet LithographyModern Semiconductor Devices for Integrated Circuits (C. Hu)Extreme UV Lithography (13nm wavelength)Slide 3-*Extreme UV Lithography (13nm wavelength)No suitable lens material at this wavelength. Optics is based on mirrors with nm flatness.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Electron Beam Writing : Electron beam(s) scans and exposed electron resist on wafer. Ready technology with relatively low throughput. Electron Projection Lithography : Exposes a complex pattern using mask and electron lens similar to optical lithography. Nano-imprint : Patterns are etched into a durable material to make a “stamp.” This stamp is pressed into a liquid film over the wafer surface. Liquid is hardened with UV to create an imprint of the fine patterns. Beyond Optical LithographyModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.4 Pattern Transfer–EtchingIsotropic etchingAnisotropic etchingModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.4 Pattern Transfer–EtchingCross-section ViewTop ViewReactive-Ion Etching SystemsGas InletRFVacuumWafersGas BaffleRFModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.4 Pattern Transfer–EtchingDry Etching (also known as Plasma Etching, or Reactive-Ion Etching) is anisotropic. Silicon and its compounds can be etched by plasmas containing F. Aluminum can be etched by Cl. Some concerns :- Selectivity and End-Point Detection - Plasma Process-Induced Damage or Wafer Charging Damage and Antenna EffectModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Scanning electron microscope view of a plasma-etched 0.16 mm pattern in polycrystalline silicon film.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.5 Doping 3.5.1 Ion ImplantationThe dominant doping method Excellent control of dose (cm-2) Good control of implant depth with energy (KeV to MeV) Repairing crystal damage and dopant activation requires annealing, which can cause dopant diffusion and loss of depth control.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.5.1 Ion ImplantationSchematic of an Ion ImplanterModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.5.1 Ion implantationPhosphorous density profile after implantationModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.5.1 Ion ImplantationModel of Implantation Doping Profile (Gaussian)Ni : dose (cm-2) R : range or depth DR : spread or sigmaModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Other Doping MethodsGas-Source Doping : For example, dope Si with P using POCl3. Solid-Source Doping : Dopant diffuses from a doped solid film (SiGe or oxide) into Si. In-Situ Doping : Dopant is introduced while a Si film is being deposited.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.6 Dopant DiffusionN : Nd or Na (cm-3) No : dopant atoms per cm2 t : diffusion time D : diffusivity, is the approximate distance of dopant diffusion Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.6 Dopant Diffusion Some applications need very deep junctions (high T, long t). Others need very shallow junctions (low T, short t). D increases with increasing temperature.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.6 Dopant DiffusionShallow Junction and Rapid Thermal Annealing After ion implantation, thermal annealing is required. Furnace annealing takes minutes and causes too much diffusion of dopants for some applications. In rapid thermal annealing (RTA), the wafer is heated to high temperature in seconds by a bank of heat lamps. In flash annealing (100mS) and laser annealing (<1uS), dopant ddiffusion is practically eliminated. Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7 Thin-Film DepositionThree Kinds of SolidCrystallinePolycrystallineExample: Silicon waferThin film of Si or metal.Thin film of SiO2 or Si3N4.AmorphousModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7 Thin-Film Deposition Advanced MOSFET gate dielectric Poly-Si film for transistor gates Metal layers for interconnects Dielectric between metal layers Encapsulation of IC Examples of thin films in integrated circuitsModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7.1 SputteringSchematic Illustration of Sputtering ProcessModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7.2 Chemical Vapor Deposition (CVD)Thin film is formed from gas phase components.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Some Chemical Reactions of CVDPoly-Si : SiH4 (g) Si (s) + 2H2 (g) Si3N4 : 3SiH2Cl2 (g)+4NH3 (g) Si3N4 (s)+6HCl(g)+6H2 (g) SiO2 : SiH4 (g) + O2 (g) SiO2 (s) + 2H2 (g) or SiH2Cl2 (g)+2N2O (g) SiO2 (s)+2HCl (g)+2N2 (g) Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Two types of CVD equipment: LPCVD (Low Pressure CVD) : Good uniformity. Used for poly-Si, oxide, nitride. PECVD (Plasma Enhanced CVD) : Low temperature process and high deposition rate. Used for oxide, nitride, etc. 3.7.2 Chemical Vapor Deposition (CVD)Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*LPCVD Systems3.7.2 Chemical Vapor Deposition (CVD)Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7.2 Chemical Vapor Deposition (CVD)PECVD SystemsCold Wall Parallel PlateHot Wall Parallel PlatePumpPlasma ElectrodesPower leadsWafersGas InletWafersGas Injection RingPumpHeater CoilModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.7.3 Epitaxy (Deposition of Single-Crystalline Film) EpitaxySelective EpitaxyModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.8 Interconnect – The Back-end ProcessModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*SEM: Multi-Level Interconnect (after removing the dielectric)3.8 Interconnect – The Back-end ProcessModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Copper InterconnectAl interconnect is prone to voids formation by electromigration. Cu has excellent electromigration reliability and 40% lower resistance than Al. Because dry etching of copper is difficult (copper etching products tend to be non-volatile), copper patterns are defined by a damascene process.3.8 Interconnect – The Back-end ProcessModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Copper Damascene ProcessChemical-Mechanical Polishing (CMP) removes unwanted materials. Barrier liner prevents Cu diffusion. 3.8 Interconnect – The Back-end ProcessModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.8 Interconnect – The Back-end ProcessPlanarization A flat surface is highly desirable for subsequent lithography and etching. CMP (Chemical-Mechanical Polishing) is used to planarize each layer of dielectric in the interconnect system. Also used in the front-end process.Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.9 Testing, Assembly, and Qualification Wafer acceptance test Die sorting Wafer sawing or laser cutting Packaging Flip-chip solder bump technology Multi-chip modules Burn-in Final test Qualification Modern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*3.10 Chapter Summary–A Device Fabrication ExampleWaferOxidationLithographyEtchingAnnealing & DiffusionAl SputteringLithographyIon ImplantationModern Semiconductor Devices for Integrated Circuits (C. Hu)nullSlide 3-*Metal etchingCVD nitride depositionLithography and etchingBack Side millingBack side metallizationDicing, wire bonding, and packaging3.10 Chapter Summary–A Device Fabrication ExampleModern Semiconductor Devices for Integrated Circuits (C. Hu)