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计算机专业英语学习

2012-10-20 50页 ppt 324KB 19阅读

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计算机专业英语学习nullComputer English Computer English Chapter 2 Organization of ComputersnullKey points: useful terms and organization of computers Difficult points: describing the organization of computersnullRequirements:1. Terms of computer hardware 2. Organization...
计算机专业英语学习
nullComputer English Computer English Chapter 2 Organization of ComputersnullKey points: useful terms and organization of computers Difficult points: describing the organization of computersnullRequirements:1. Terms of computer hardware 2. Organization of computers and their functions3. 掌握专业词汇的构成规律,特别是常用词缀及复合词的构成 nullNew Words & Expressions: instruction cycle 指令周期 decode vt.解码, 译解 bus n. 总线 pins n.插脚, 管脚 uppermost adj.最高的;adv.在最上 address bus 地址总线 data bus 数据总线 via prep.经, 通过, 经由 multibit 多位 bidirectional 双向的 unidirectional 单向的 hierarchy n.层次,层级 microprocessor n.微处理器 register n.寄存器 timing n.定时;时序;时间选择 synchronize vt.使...同步 assert vt.主张,发出 deassert vt. 撤销 trigger vt.引发, 引起, 触发 map v.映射 port n.端口2.1 Basic Organization of Computers Abbreviations: CPU(Central Processing Unit) 中央处理器 I/O(Input/Output) 输入输出(设备)null2.1 Basic Organization of ComputersFig.2-1 Generic computer organizationnull2.1 Basic Organization of ComputersMost computer systems, from the embedded controllers found in automobiles and consumer appliances to personal computers and mainframes, have the same basic organization. This organization has three main components: the CPU, the memory subsystem, and the I/O subsystem. The generic organization of these components is shown in Figure 2-1.大多数计算机系统,从汽车和日用电器中的嵌入式控制器到个人计算机和大型主机,都具有相同的基本组成。其基本组成包括三个主要部件:CPU、存储器子系统和I/O子系统。这些部件的一般组成如图2-1所示。nullPhysically, a bus is a set of wires. The components of the computer are connected to the buses. To send information from one component to another, the source component outputs data onto the bus. The destination component then inputs this data from the bus. As the complexity of a computer system increases, it becomes more efficient (in terms of minimizing connections) at using buses rather than direct connections between every pair of devices. Buses use less space on a circuit board and require less power than a large number of direct connections. They also require fewer pins on the chip or chips that comprise the CPU.2.1.1 System Buses从物理上来说,总线就是一组导线。计算机的部件就是连在总线上的。为了将信息从一个部件传到另一个部件,源部件先将数据输出到总线上,然后目标部件再从总线上接受这些数据。随着计算机系统复杂性的不断增长,使用总线比每个设备对之间直接连接要有效得多(就减少连接数量而言)。与大量的直接连接相比,总线使用较少的电路板空间,耗能更少,并且在芯片或组成CPU的芯片组上需要较少的引脚。nullThe system shown in Figure 2-1 has three buses. The uppermost bus in this figure is the address bus. When the CPU reads data or instructions from or writes data to memory, it must specify the address of the memory location it wishes to access. It outputs this address to the address bus; memory inputs this address from the address bus and use it to access the proper memory location. Each I/O devices, such as a keyboard, monitor, or disk drive, has a unique address as well. When accessing an I/O device, the CPU places the address of the device on the address bus. Each device can read the address off of the bus and determine whether it is the device being accessed by the CPU. Unlike the other buses, the address bus always receives data from the CPU; the CPU never reads the address bus.图2-1所示的系统包括三组总线。最上面的是地址总线。当CPU从存储器读取数据或指令,或写数据到存储器时,它必须指明将要访问的存储器地址。CPU将地址输出到地址总线上,而存储器从地址总线上读取地址,并且用它来访问正确的存储单元。每个I/O设备,比如键盘、显示器或者磁盘,同样都有一个唯一的地址。当访问某个I/O设备时,CPU将此设备的地址放到地址总线上。每一个设备均从总线上读取地址并且判断自己是否就是CPU正要访问的设备。与其他总线不同,地址总线总是从CPU上接收信息,而CPU从不读取地址总线。2.1.1 System BusesnullData is transferred via the data bus. When the CPU fetches data from memory, it first outputs the memory address on its address bus. Then memory outputs the data onto the data bus; the CPU can then read the data from the data bus. When writing data to memory, the CPU first outputs the address onto the address bus, then outputs the data onto the data bus. Memory then reads and stores the data at the proper location. The processes for reading data from and writing data to the I/O devices are similar.数据是通过数据总线传送的。当CPU从存储器中取数据时,它首先把存储器地址输出到地址总线上,然后存储器将数据输出到数据总线上,这样CPU就可以从数据总线上读取数据了。当CPU向存储器中写数据时,它首先将地址输出到地址总线上,然后把数据输出到数据总线上,这样存储器就可以从数据总线上读取数据并将它存储到正确的单元中。对I/O设备读写数据的过程与此类似。2.1.1 System BusesnullThe control bus is different from the other two buses. The address bus consists of n lines, which combine to transmit one n-bit address value. Similarly, the lines of the data bus work together to transmit a single multibit value. In contrast, the control bus is a collection of individual control signals. These signals indicate whether data is to be read into or written out of the CPU, whether the CPU is accessing memory or an I/O device, and whether the I/O device or memory is ready to transfer data. Although this bus is shown as bidirectional in Figure 2-1, it is really a collection of (mostly) unidirectional signals. Most of these signals are output from the CPU to the memory and I/O subsystems, although a few are output by these subsystems to the CPU. We examine these signals in more detail when we look at the instruction cycle and the subsystem interface.控制总线与以上两种总线都不相同。地址总线由n根线构成,n根线联合传送一个n位的地址值。类似地,数据总线的各条线合起来传输一个单独的多位值。相反,控制总线是单根控制信号的集合。这些信号用来指示数据是要读入CPU还是要从CPU写出,CPU是要访问存储器还是要访问I/O设备,是I/O设备还是存储器已就绪要传送数据等等。虽然图2-1所示的控制总线看起来是双向的,但它实际上(主要)是单向(大多数都是)信号的集合。大多数信号是从CPU输出到存储器与I/O子系统的,只有少数是从这些子系统输出到CPU的。在介绍指令周期和子系统接口时,我们将详细地讨论这些信号。2.1.1 System BusesnullA system may have a hierarchy of buses. For example, it may use its address, data, and control buses to access memory, and an I/O controller. The I/O controller, in turn, may access all I/O devices using a second bus, often called an I/O bus or a local bus. 一个系统可能具有分层次的总线。例如,它可能使用地址、数据和控制总线来访问存储器和I/O控制器。I/O控制器可能依次使用第二级总线来访问所有的I/O设备,第二级总线通常称为I/O总线或者局部总线。2.1.1 System BusesnullThe instruction cycle is the procedure a microprocessor goes through to process an instruction. First the microprocessor fetches, or reads, the instruction from memory. Then it decodes the instruction, determining which instruction it has fetched. Finally, it performs the operations necessary to execute the instruction. (Some people also include an additional element in the instruction cycle to store results. Here, we include that operation as part of the execute function.) Each of these functions--fetch, decode, and execute--consists of a sequence of one or more operations.指令周期是微处理器完成一条指令处理的步骤。首先,微处理器从存储器读取指令,然后将指令译码,辩明它取的是哪一条指令。最后,它完成必要的操作来执行指令(有人认为在指令周期中还要包括一个附加的步骤来存储结果,这里我们把该操作当作执行功能的一部分)。每一个功能——读取、译码和执行都包括一个或多个操作。 2.1.2 Instruction CyclenullLet's start where the computer starts, with the microprocessor fetching the instruction from memory. First, the microprocessor places the address of the instruction on to the address bus. The memory subsystem inputs this address and decodes it to access the sired memory location. (We look at how this decoding occurs when we examine the memory subsystem in more detail later in this chapter.)我们从微处理器从存储器中取指令开始讲述。首先,微处理器把指令的地址放到地址总线上,然后,存储器子系统从总线上输入该地址并予以译码,去访问指定的存储单元。(译码是如何进行的,我们将在后面的章节中介绍存储器子系统是更为详细的讨论。) 2.1.2 Instruction CyclenullAfter the microprocessor allows sufficient time for memory to decode the address and access the requested memory location, the microprocessor asserts a READ control signal. The READ signal is a signal on the control bus which the microprocessor asserts when it is ready to read data from memory or an I/O device. (Some processors have a different name for this signal, but all microprocessors have a signal to perform this function.) Depending on the microprocessor, the READ signal may be active high (asserted - 1) or active low (asserted - 0).当微处理器为存储器留出充足的时间来对地址译码和访问所需的存储单元之后,微处理器发出一个读(READ)控制信号。当微处理器准备好可以从存储器或是I/O设备读数据时,它就在控制总线上发一个读信号。(一些处理器对于这个信号有不同的名字,但所有处理器都有这样的信号来执行这个功能。)根据微处理器的不同,读信号可能是高电平有效(信号=1),也可能是低电平有效(信号=0)。 2.1.2 Instruction CyclenullWhen the READ signal is asserted, the memory subsystem places the instruction code to be fetched onto the computer system's data bus, The microprocessor then inputs this data from the bus and stores it in one of its internal registers. At this point, the microprocessor has fetched the instruction.读信号发出后,存储器子系统就把要取的指令码放到计算机的数据总线上,微处理器就从数据总线上输入该数据并且将它存储在其内部的某个寄存器中。至此,微处理器已经取得了指令。2.1.2 Instruction CyclenullNext, the microprocessor decodes the instruction. Each instruction may require a different sequence of operations to execute the instruction. When the microprocessor decodes the instruction, it determines which instruction it is in order to select the correct sequence of operations to perform. This is done entirely within the microprocessor; it does not use the system buses.接下来,微处理器对这条指令译码。每一条指令可能要有不同的操作序列来执行。当微处理器对该指令译码是,它确定处理的是哪一条指令以便选择正确的操作序列去执行。这一步完全在微处理器内完成,不需要使用系统总线。 2.1.2 Instruction CyclenullFinally, the microprocessor executes the instruction. The sequence of operations to execute the instruction varies from instruction to instruction. The execute routine may read data from memory, write data to memory, read data from or write data to an I/O device, perform only operations within the CPU, or perform some combination of these operations. We now look at how the computer performs these operations from a system perspective.最后,微处理器执行该指令。指令不同,执行的操作序列也不同。执行过程可以是从存储器读取数据,写数据到存储器,读或写数据到I/O设备,执行CPU内部操作或者执行多个上述操作的组合。下面我们从系统的角度来看计算机是怎样执行这些操作的。 2.1.2 Instruction CyclenullTo read data from memory, the microprocessor performs the same sequence of operations it uses to fetch an instruction from memory. After all, fetching an instruction is simply reading it from memory. Figure 2-2(a) shows the timing of the operations to read data from memory.微处理器从存储器读取数据所执行的操作序列,同从存储器中去一条指令是一样的。毕竟取指令就是简单地从存储器中读取它。图2-2(a)显示了从存储器中读取数据的操作时序。 2.1.2 Instruction CyclenullIn Figure 2-2, notice the top symbol, CLK. This is the computer system clock; the microprocessor uses the system clock to synchronize its operations. The microprocessor places the address onto the bus at the beginning of a clock cycle, a 0/1 sequence of the system clock. One clock cycle later, to allow time for memory to decode the address and access its data, the microprocessor asserts the READ Signal. This causes memory to place its data onto the system data bus. During this clock cycle, the microprocessor reads the data off the system bus and stores it in one of its registers. At the end of the clock cycle it removes the address from the address bus and deasserts the READ signal. Memory then removes the data from the data bus, completing the memory read operation.在图2-2中,注意最上面的符号CLK,它是计算机的系统时钟,微处理器用系统时钟使其操作同步。在一个时钟周期(系统时钟的0/1序列)的开始位置,微处理器将地址放到总线上。一个时钟周期(允许存储器对地址译码和访问数据的时间)之后,微处理器才发出读信号。这使得存储器将数据放到数据总线上。在这个时钟周期之内,微处理器从系统总线上读取数据,并存储到它的某个寄存器中。在这个时钟周期结束时,微处理器撤消地址总线上的地址,并撤消读信号。然后存储器从数据总线上撤消数据,也就完成了存储器的读操作。2.1.2 Instruction CyclenullThe timing of the memory write operation is shown in Figure 2-2(b). The processor places the address and data onto the system buses during the first clock cycle. The microprocessor then asserts a WRITE control signal (or its equivalent) at the start of the second clock cycle. Just as the READ signal causes memory to read data, the WRITE signal triggers memory to store data. Some time during this cycle, memory writes the data on the data bus to the memory location whose address is on the address bus. At the end of this cycle, the processor completes the memory write operation by removing the address and data from the system buses and deasserting the WRITE signal.存储器写操作的时序如图2-2(b)所示。在第一个时钟周期,处理器将地址和数据放到总线上,然后在第二个时钟周期开始 时发出一个写(WRITE)控制信号(或与之等价的信号)。像读信号促使存储器读取数据一样,写信号促使存储器存储数据。在这个时钟周期的某个时刻,存储器将数据总线上的数据写入地址总线指示的存储单元内。当这个时钟周期结束,微处理器从系统总线上撤消地址、数据及写信号后,就完成了存储器的写操作。 2.1.2 Instruction CyclenullThe I/O read and write operations are similar to the memory read and write operations. A processor may use either memory mapped I/O or isolated I/O. If the processor supports memory mapped I/O, it follows the same sequences of operations to input or output data as to read data from or write data to memory, the sequences shown in Figure 2-2. (Remember, in memory mapped I/O, the processor treats an I/O port as a memory location, so it is reasonable to treat an I/O data access the same as a memory access.) Processors that use isolated I/O follow the same process but have a second control signal to distinguish between I/O and memory accesses. (CPUs that use isolated I/O can have a memory location and an I/O port with the same address, which makes this extra signal necessary.) I/O的读写操作与存储器的读写操作类似。处理器可以使用存储器影射I/O或者是单独I/O。如果处理器支持存储器影射I/O,则它遵循从存储器读写数据同样的操作顺序,该顺序如图2-2所示(记住,在存储器影射I/O中,处理器把一个I/O端口当作某个存储单元,当然I/O的数据访问同存储器的数据访问一样的)。使用单独I/O的处理器遵循同样的处理过程,但是另有一个控制信号用以区别是I/O访问还是存储器访问(使用单独I/O的CPU允许一个存储单元和某个I/O端口具有相同的地址,因此需要这一额外的信号加以区分)。 2.1.2 Instruction CyclenullFinally, consider instructions that are executed entirely within the microprocessor. The INAC instruction of the Relatively Simple CPU, and the MOV r1, r2 instruction of the 8085 microprocessor, can be executed without accessing memory or I/O devices. As with instruction decoding, the execution of these instructions does not make use of the system buses.最后,考虑一下完全在微处理器内部执行的指令。相对简单CPU的INAC指令和8085的MOV r1,r2指令的执行都不要访问存储器和I/O设备。按照指令译码的结果,这些指令的执行不会用到系统总线。 2.1.2 Instruction CyclenullNew Words & Expressions: latch v.闭锁,锁存 program counter 程序计数器 instruction register 指令寄存器 operand n. 操作数 increment n.增量,加1 flag register 标志寄存器 pipeline n.流水线 microsequenced 微层序的 local bus 局部总线 Abbreviations: ALU (Arithmetic Logic Unit) 算术逻辑单元 2.2 CPU ORGANIZATIONnullThe CPU controls the computer. It fetches instructions from memory, supplying the address and control signals needed by memory to access its data. The CPU decodes the instruction and controls the execution procedure. It performs some operations internally, and supplies the address, data, and control signals needed by memory and I/O devices to execute the instruction. Nothing happens in the computer unless the CPU causes it to happen. CPU控制整个计算机。它从存储器中取指令,提供存储器需要的地址和控制信号。CPU对指令译码并且控制整个执行过程。它执行一些内部操作,并且为存储器和I/O设备执行指令提供必要的地址、数据和控制信号。除非CPU激发,否则,计算机什么事情都不会发生。 2.2 CPU ORGANIZATIONnullInternally, the CPU has three sections, as shown in Figure 2-3. The register sections, as its name implies, includes a set of registers and a bus or other communication mechanism. The registers in a processor's instruction set architecture are found in this section of the CPU. The system address and data buses interact with this section of the CPU. The register section also contains other registers that are not directly accessible by the programmer. The relatively simple CPU includes registers to latch the address being accessed in memory and a temporary storage register, as well as other registers that are not a part of its instruction set architecture.CPU内部有三大分区,如图2-3所示。寄存器区,顾名思义,它包括一组寄存器、一条总线或其他通信机制。微处理器指令集结构中的寄存器就属于CPU的这一分区。系统的地址和数据总线与寄存器交互。此分区还包括程序员不能直接访问的一些寄存器。相对简单CPU含有寄存器用以锁存正在访问的存储器地址,还有暂存器以及指令集结构中没有的其他寄存器等。 2.2 CPU ORGANIZATIONnullDuring the fetch portion of the instruction cycle, the processor first outputs the address of the instruction onto the address bus. The processor has a register called the program counter; the CPU keeps the address of the next instruction to be fetched in this register. Before the CPU outputs the address onto the system's address bus, it retrieves the address from the program counter register. At the end of the instruction fetch, the CPU reads the instruction code from the system data bus. It stores this value in an internal register, usually called the instruction register or something similar.在指令周期的取指阶段,处理器首先将指令的地址输出到地址总线上。处理器有一个寄存器叫做程序计数器,CPU将下一条要取的指令的地址存放在程序计数器中。在CPU将地址输出到系统的地址总线之前,必须从程序计数器中取出该地址。在指令结束前,CPU从系统时局总线上读取指令码,它把该指令码存储在某个内部寄存器中,该寄存器通常称作指令寄存器或其他相似的名字。 2.2 CPU ORGANIZATIONnullThe arithmetic logic unit or ALU performs most arithmetic and logical operations, such as adding or ADDing values. It receives its operands from the register section of the CPU and stores its results back in the register section. Since the ALU must complete its operations within a single clock cycle, it is constructed using only combinatorial logic. The ADD instructions in the relatively simple CPU and the 8085 microprocessor use the ALU during their executions.算术逻辑单元执行大部分的算术逻辑运算,如加法、逻辑与等运算。它从CPU的寄存器取得操作数,然后将运算结果再存回到寄存器区。由于必须在一个时钟周期内完成操作,因此ALU只采用组合逻辑构造而成。相对简单CPU和8085微处理器中的ADD指令在执行中都有使用ALU。 2.2 CPU ORGANIZATIONnullJust as the CPU controls the computer (in addition to its other functions), the control unit controls the CPU. This unit generates the internal control signals that cause registers to load data, increment or clear their contents, and output their contents, as well as cause the ALU to perform the correct function. These signals are shown as control signals in Figure 2-3. The control unit receives some data values from the register unit, which it uses to generate the control signals. This data includes the instruction code and the values of some flag registers. 同CPU控制整个计算机(除了其他功能外)一样,控制单元控制着CPU。这个单元产生内部控制信号,促使寄存器装载数据,自动加1或清零,输出它的内容,使得ALU完成正确的操作等等。这些信号作为控制信号显示在图2-3中。控制单元从寄存器区取得一些数据用以产生控制信号,这些数据包括指令码和某些标志寄存器的值。 2.2 CPU ORGANIZATIONnullThe control unit also generates the signals for the system control bus, such as the READ, WRITE, and signals. A microprocessor typically performs a sequence of operations to fetch, decode, and execute an instruction. By asserting these internal and external control signals in the proper sequence, the control unit causes the CPU and the rest of the computer to perform the operations needed to correctly process instructions. 2.2 CPU ORGANIZATION控制单元也产生系统控制总线上的信号,例如READ,WRATE, 信号等。典型的一个微处理器执行取指令、译指令和执行指令等一系列的操作。通过以正确的顺序激发这些内部或外部控制信号,控制单元使CPU和计算机的其余部分完成正确处理指令所需要的操作。nullThis description of the CPU is incomplete. Current processors have more complex features that improve their performance. One such mechanism, the instruction pipeline, allows the CPU to fetch one instruction while simultaneously executing another instruction. 2.2 CPU ORGANIZATION以上对CPU的描述并不完整。现在的处理器拥有更加复杂的特征以提高其性能。这些机制中有一种是指令流水线技术,它允许CPU在执行一条指令的同时取出另一条指令。nullIn this section we have introduced the CPU from a system perspective, but we have not discussed its internal design. We examine the registers, data paths, and control unit, all of which act together to cause the CPU to properly fetch, decode, and execute instructions. Microsequenced CPUs have the same registers, ALUs and data paths as hardwired CPUs, but completely different control units. 本节我们从系统的角度介绍了CPU,但我们还没有讨论它的内部设计。我们描述了CPU的寄存器、数据通路、控制单元等,所有部件一起工作使CPU正确地读取、译码和执行指令。微层序CPU具有同硬连线CPU一样的寄存器、ALU和数据通路,但二者控制单元完全不同。 2.2 CPU ORGANIZATIONnull2.3 Memory Subsystem Organization and InterfacingNew Words & Expressions: multibyte n.多字节 MB n.兆字节 shut off n.切断,关闭 enable n..使能 tri-state 三态 tri-stated 高阻态 dimension n.尺度, 维(数) configuration n.构造, 结构, 配置 as far as 尽;就;至于 high-order 高位 low-order 低位 interleaving n.交叉,交错 contiguous adj.邻近的, 接近的 assign vt.分配, 指派 big endian 高位优先 little endian 低位优先 hexadecimal adj.十六进制的;n.十六进制 alignment n.对齐方式 leftmost adj.最左边的 rightmost adj.最右边的,最右面的 consecutive adj.连续的, 联贯的 cache n.高速缓冲 virtual memory 虚拟存储器 buffer n.缓冲器 ROM(Read Only Memory) 只读存储器 RAM(Random Access Memory) 随机存取存贮器 RISC(Reduced Instruction Set Computer) 精简指令集计算机null2.3 Memory Subsystem Organization and InterfacingIn this section we examine the construction and functions of the memory subsystem of a computer. We review the different types of physical memory and the internal organization of their chips. We discuss the construction of the memory subsystem, as well as multibyte word organizations and advanced memory organizations.本节我们将讨论计算机中存储器子系统的结构和功能。我们将会回顾不同类型的物理存储器及其芯片的内部组成,讨论存储器子系统的结构,以及多字节的组织和高级存储器的组成。null2.3.1 Types of MemoryThe internal organizations of ROM and RAM chips are similar. To illustrate the simplest organization, a linear organization, consider an 82 ROM chip. For simplicity, programming components are not shown. This chip has three address inputs and two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations.存储器芯片有两种类型:只读存储器(ROM)和随机存取存储器(RAM)。只读存储器芯片是为数据(此数据可包括程序的指令)只读的应用而设计的。这些芯片在加入系统之前,就已经被某个外部编程器而装好数据了。这个工作一旦完成,其数据通常不再改变。ROM芯片总是保存有数据,甚至在芯片断电以后。例如,一个微波炉的嵌入式控制器可以连续运行一个不变的程序。这个程序就存储在一片ROM上。nullRandom Access
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