桂林电子科技大学EDA实验五

实验五 有限状态机 一、实验目的：本次实验通过 Verilog 硬件语言编写摩尔型有限状态 机和米勒型有限状态机，掌握采用有限状态机产生各种控制信号的原 理，熟悉如何选用合适的有限状态机进行电路设计，通过实验进一步 了解原理图编辑方法和仿真方法。 二、实验要求： 1、利用 Verilog硬件语言，参考提供的源程序，设计一个采用摩尔 型有限状态机实现的流水灯控制程序； 2、利用 Verilog硬件语言，参考提供的源程序，设计一个采用米勒 型有限状态机实现的串行口发送程序； 3、利用 Verilog硬件语言，参考提供的源程序，设计一个采用米勒 型有限状态机实现的串行口接收程序； 4、利用原理图编辑方法，将串行口发送和接收模块进行连接，实 现完整的串行通信电路，并对该电路进行仿真。 摩尔型有限状态机实现的流水灯源程序 module sled(clk,led); input clk; output [7:0] led; reg [7:0] led; reg[2:0] state; parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101, s6=3'b110, s7=3'b111; always @(posedge clk) case(state) s0: begin state<=s1; led<=8'b00000001; end s1: begin state<=s2; led<=8'b00000010; end s2: begin state<=s3; led<=8'b00000100; end s3: begin state<=s4; led<=8'b00001000; end s4: begin state<=s5; led<=8'b00010000; end s5: begin state<=s6; led<=8'b00100000; end s6: begin state<=s7; led<=8'b01000000; end s7: begin state<=s0; led<=8'b10000000; end endcase endmodule 米勒型有限状态机实现的串行口发送源程序 module s_tx(clk,en,dain,txd); input clk,en; input[7:0] dain; output txd; reg [7:0] da_temp; reg txd; reg [3:0] state; parameter swait=4'b0000, star=4'b0001, s1=4'b0010, s2=4'b0011, s3=4'b0100, s4=4'b0101, s5=4'b0110, s6=4'b0111, s7=4'b1000, s8=4'b1001, stop=4'b1010; always @(posedge en) da_temp<=dain; always @(posedge clk) if (!en) begin state<=swait; txd<=1; end else case(state) swait: begin state<=star;txd<=1; end star: begin state<=s1; txd<=0; end s1: begin state<=s2; txd<=da_temp[7]; end s2: begin state<=s3; txd<=da_temp[6]; end s3: begin state<=s4; txd<=da_temp[5]; end s4: begin state<=s5; txd<=da_temp[4]; end s5: begin state<=s6; txd<=da_temp[3]; end s6: begin state<=s7; txd<=da_temp[2]; end s7: begin state<=s8; txd<=da_temp[1]; end s8: begin state<=stop; txd<=da_temp[0]; end stop: begin state<=stop; txd<=1; end endcase endmodule 米勒型有限状态机实现的串行口接收源程序 module s_rx(clk,dain,daout); input clk,dain; output [7:0] daout; reg [7:0] daout; reg [7:0] da_temp; reg [3:0] state; parameter star=4'b0000, s1=4'b0010, s2=4'b0011, s3=4'b0100, s4=4'b0101, s5=4'b0110, s6=4'b0111, s7=4'b1000, s8=4'b1001, stop=4'b1010; always @(negedge clk) case (state) star: if (dain) state<=star; else state<=s1; s1:begin state<=s2; da_temp[7]<=dain; end s2:begin state<=s3; da_temp[6]<=dain; end s3:begin state<=s4; da_temp[5]<=dain; end s4:begin state<=s5; da_temp[4]<=dain; end s5:begin state<=s6; da_temp[3]<=dain; end s6:begin state<=s7; da_temp[2]<=dain; end s7:begin state<=stop; da_temp[1]<=dain; end stop:if (!dain) state<=stop; else begin state<=star; daout<=da_temp; end endcase endmodule 串行口通信系统原理图电路