SEED-XDSusb Readme

SEED-XDSUSB Emulator Pod 2003 DSP Development Systems Installation Guide SEED-XDSUSB Emulator Pod Installation Guide May 2003 SEED INTERNATIONAL LTD. Rm 302, CATIC, No. 44 Tsun Yip St, KT, HK Tel: +852 34268098 Fax: +852 34264806 sales@seeddsp.com www.seeddsp.com Contents 1 Installing the SEED-XDSUSB Emulator Pod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Lists the hardware and software you’ll need to install the XDSUSB emulator pod. 1.1 What You’ll Need . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Hardware checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Software checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Step 1: Connecting the Emulator to your PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Step 2: Selecting emulate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Step 3: Connecting the Emulator to Your Target System . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 XDSUSB's LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.6 WAIT-IN-RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2 Specifications for Your Target System’s Connection to the Emulator . . . . . . . . . . . . . . . 2-1 Contains information about constructing a 14-pin connector on your target system and information about connecting the emulator to the target system. 2.1 Designing Your Target System’s JTAG Emulator Connector (14-pin Header) . . . . . . . . 2-2 2.2 Designing Your Target System's MPSD Emulator Connector (14-pin Header) . . . . . . . . 2-3 2.3 Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Emulator Pod Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 JTAG Emulator Pod Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 MPSD Emulator Pod Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.7 Buffering Signals Between the JTAG Emulator and the Target System . . . . . .. . . . . . . 2-9 2.8 Buffering Signals Between the MPSD Emulator and the Target System . . . . . . . . . . . 2-12 2.9 Mechanical Dimensions for the 14-Pin Emulator Connector . . . . . . . . . . . . . . . . . . . . . 2-14 1-1 Chapter 1 Installing the SEED-XDSUSB Emulator Pod This chapter helps you install the SEED-XDSUSB emulator pod on a PC running Windows 98/2000/XP. When you complete the installation. Topic Page 1.1 What You’ll Need 1-2 Hardware checklist 1-2 Software checklist 1-2 1.2 Step 1: Connecting the Emulator to your PC 1-3 1.3 Step 2: Selecting emulate mode 1-4 1.4 Step 2: Connecting the Emulator to Your Target System 1-4 1.5 XDSUSB's LED 1-5 1.6 WAIT-IN-RESET 1-5 SEED International Ltd. 1-2 XDSUSB Emulator Pod Installation Guide 1.1 What You’ll Need The following checklists detail items that are shipped with the XDSUSB and additional items you’ll need to use these tools. Hardware checklist __ host An IBM PC/AT or 100% compatible PC or laptop with a hard-disk system and a 1.44M floppy-disk drive with USB port __ memory Minimum of 32MB __ display Color VGA or LCD __ emulator module XDSUSB USB Port emulator __ target system A board with a TI DSP or Microcontroller and power supply __ connector to 14-pin connector (two rows of seven pins) --- see Chapter 2 for target system more information about this connector Software checklist __ operating system Win 98, Win 2000, or Win XP __ software tools Compiler/assembler/linker for DSP or Microcontroller __ debugger Code Composer Studio or TI HLL Debugger __ drivers drivers for Code Composer/Code Composer Studio SEED International Ltd. 1-3 1.2 Step 1:Installing the XDSUSB JTAG Emulator This section contains the steps for installing the XDSUSB JTAG Emulator. XDSUSB Installation Checklist To install the XDSJTAG emulator execute the following checklist: ❏ Turn off the power to your target board. ❏ Insert the USB Driver CD-ROM in the computers CD-ROM drive and install the device drivers. Code Composer/Studio should be installed already. ❏ Connect the supplied USB cable to your PC or laptop. If you connect the USB cable to a USB hub be sure the hub is connected to the PC or laptop and power is applied to the hub. ❏ Connect the supplied USB cable to your XDSUSB emulator. Do not connect or disconnect the 14-pin cable while the target system is powered up. Target Cable Connectors: Be very careful with the target cable connectors. connect them gently; don’t force them into position, or you may damage the connectors. WARNING SEED International Ltd. 1-4 XDSUSB Emulator Pod Installation Guide 1.3 Step 2: Selecting XDSUSB's emulate mode Figure 1-1 shows how you select the XDSUSB's emulate mode. You must set it to the right mode according the DSP kind on your target system. In most cases, the mode will be JATG. For C30/C31/C32, it should be MPSD. Figure 1-1. Selecting XDSUSB's emulate mode JTAG插座MPSD插座 MPSD方式 JTAG方式 仿真电缆 JTAG插座MPSD插座 MPSD方式 JTAG方式 仿真电缆 14 pin cable Emulator pod USB Cable USB port DSP baord 14 pin connector C2000/C3x/C5000/C6000 DSP Target active LED SEED-XDSUSB JTAG slotMPSD slot MPSD mode JTAG mode 14 pin cable 1.4 Step 3: Connecting the XDSUSB to Your Target System Figure 1-2 shows how you connect the XDSUSB emulator pod with USB cable to your target system. In most cases, the target system will be a target board of your own design. Figure 1-2. Connecting the XDSUSB Emulator Pod to Your Target System SEED International Ltd. 1-5 1.5 XDSUSB's LED The XDSUSB has 1 red Light Emitting Diode (LED). This LED indicates a connect has been made to the target system. 1.6 WAIT-IN-RESET Newer TI DSPs (e.g. TMS320C27x) have a feature called Wait-In-Reset. When the XDSUSB detects the loss of target poser it will drive EMU0 to 0 volts. When the target system is powered on and EMU0 = 0 volts, EMU1 = Vcc, and TRSTn = 0 volts then the DSP will wait in reset until the debugger is started. On processors that do not support Wait-In-Reset” pulling EMU0 should have no effect. EMU0 is tri-stated within 20 milliseconds after TRST returns high. A 100 ohm resistor is included in the event that the target system is driving this signal. Normally this signal is pulled high on the target system with a 4.7K ohm or larger resistor. 2-1 Chapter 2 Specifications for Your Target System’s Connection to the Emulator This chapter contains information about connecting your target system to the emulator. Your target system must use a special 14-pin connector for proper communication with the emulator. Topic Page 2.1 Designing Your Target System’s JTAG Emulator Connector (14-pin Header) 2-2 2.8 Buffering Signals Between the MPSD Emulator and 2.9 Mechanical Dimensions for the 14-Pin Header 2-14 the Target System 2-12 2.7 Buffering Signals Between the JTAG Emulator and the Target System 2-9 2.3 Bus Protocol 2-4 Connector (14-pin Header) 2-3 2.2 Designing Your Target System's MPSD Emulator 2.6 MPSD Emulator Pod Signal Timing 2-8 2.5 JTAG Emulator Pod Signal Timing 2-7 2.4 Emulator Pod Logic 2-5 SEED International Ltd. 2-2 XDSUSB Emulator Pod Installation Guide 2.1 Designing Your Target System’s JTAG Emulator Connector (14-pin Header) Certain devices support emulation through a dedicated emulation port. This port is a superset of the IEEE 1149.1 (JTAG) standard and is accessed by the emulator. To perform emulation with the emulator, your target system must have a 14-pin header 2 rows of 7 pins) with the connections that are shown in Figure 2-1. Table 1 describes the emulation signals. Figure 2-1. 14-Pin Header Signals and Header Dimensions Table 1: 14-Pin Header Signal Description Signal Description EmulatorState Target State TMS JTAG test mode select. Output Input TDI JTAG test data input. Output Input TDO JTAG test data output. Input Output TCK JTAG test clock. TCK is a 10-MHz clock source from the emulation pod. This signal can be used to drive the system test clock. Output Input TRST- JTAG test reset. Output Input EMUO Emulation pin 0. Input I/O EMU1 Emulation pin 1. Input I/O PD Presence detect. Indicates that the emula- tion cable is connected and that the target is powered up. PD should be tied to +5 volts in the target system. Input Output TCK_RET JTAG test clock return. Test clock input to the emulator. May be a buffered or unbuf- fered version of TCK. Input Output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TMS TDI PD (+5V) TDO TCK-RET TCK EMU0 TRST- GND no pin (key) GND GND GND EMU1 Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal SEED International Ltd. 2-3 2.2 Designing Your Target System’s MPSD Emulator Connector (14-pin Header) The ‘C3x devices support complete emulation through a dedicated serial scan path port. This port uses a modular port scan technology (MPSD). For the application target system to communicate with the EMU320C3x your target system must have a 12-pin header(2x6). The pin signal assignments are shown in figure 2-2. Pin 8 is removed for keying purposes. Note: The header is 14-pin and two pins are not used. Figure 2-2. 12-Pin Header Signals and Header Dimensions Note: Signals EMU0, EMU1, EMU2 should always be pulled up with a separate 20k ohm resistors to Vcc. Position pin 8 will be plugged to prevent improper connection. Pin 8 is present in the cable and is grounded. Table 2: 12-Pin Header Signal Description EMU320C3X Signal Description ‘C30 Pin Number ‘C31 Pin Number ‘C32 Pin Numbers EMU0 Emulation Pin 0 F14 124 14 EMU1 Emulation Pin 1 E15 125 17 EMU2 Emulation Pin 2 F13 126 18 EMU3 Emulation Pin 3 E14 123 13 H3 ‘C3x H3 A1 82 108 PD Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to +5 volts in the target system. 1 2 3 4 5 6 7 8 9 10 11 12 EMU1 GND no pin (key) GND GND GND EMU0 Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal GND EMU2 EMU3 H3 PD(Vcc) 2.3 Bus Protocol The IEEE 1149.1 specification covers the requirements for JTAG bus slave devices (such as the TMS32OC5000 family) and provides certain rules, summarized as follows: __ The TMS/TDI inputs are sampled on the rising edge of the TCK signal of the device. __ The TDO output is clocked from the falling edge of the TCK signal of the device When JTAG devices are daisy-chained together, the TDO of one device has approximately a half TCK cycle set up to the next device’s TDI signal. This type of timing scheme minimizes race conditions that would occur if both TDO and TDI were timed from the same TCK edge. The penalty for this timing scheme is a reduced TCK frequency. The IEEE 1149.1 specification does not provide rules for JTAG bus master (emulator) devices. Instead, it states that it expects a bus master to provide bus slave compatible timings. The emulator provides timings that meet the bus slave rules and also provides an optional timing mode that allows you to run the emulation at a much higher frequency for improved performance. SEED International Ltd. 2-4 XDSUSB Emulator Pod Installation Guide SEED International Ltd. 2-5 2.4 Emulator Pod Logic Figure 2-3 shows a portion of the emulator cable pod. These are the functional features of the emulator pod: __ Signal TCK is driven with a CPLD device. Because of the high current drive (32/64 mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied to TCK_RET, then you can use the parallel terminator in the pod. __ Signals TMS and TDI can be generated from the failing edge of TCK_RET, according to the IEEE 1149.1 bus slave device timing rules. They can also be driven from the rising edge of TCK_RET, which allows a higher TCK_RET frequency. The default is o match the IEEE 1149.1 slave device timing rules. This is an emulator software option that can be selected when the emulator is invoked. In general, single-processor applications can benefit from the higher clock frequency. However, in multiprocessing applications, you may wish to use the IEEE 1149.1 bus slave timing mode to minimize emulation system timing constraints. __ Signals TMS, TCK, and TDI are series-terminated to reduce signal reflections. __ A 10-MHz test clock source is provided. You may also provide your own test clock for greater flexibility. . Figure 2-3. Emulator Pod Interface TDO(Pin 7) EMU1(Pin 14) EMU0(Pin 13) CPLD Diode 33 33 33 TCK_RET(Pin 9) PD(Pin 5) GND(Pin 4) GND(Pin 6) GND(Pin 8 GND(Pin 10) GND(Pin 12) TMS(Pin 1) TDI(Pin 3) TCK(Pin 11) TRST-(Pin 2) CPLD Diode 33 33 33 PD(Pin 7) EMU0(Pin 3) GND(Pin 4) GND(Pin 6) GND(Pin 8 GND(Pin 10) GND(Pin 12) EMU1(Pin 1) EMU2(Pin 5) EMU3(Pin 9) H3(Pin 11) GND(Pin 2) SEED International Ltd. 2-6 XDSUSB Emulator Pod Installation Guide SEED International Ltd. 2-7 2.5 JTAG Emulator Pod Signal Timing Figure 2-4 shows the signal timings for the emulator. Table 3 defines the timing parameters for the emulator. The timing parameters are calculated from standard data sheet parts used in the emulator and cable pod. These parameters are for reference only. Spectrum Digital does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system test clock source. Figure 2-4. Emulator Pod Timings Table 3: JTAG Emulator Pod Timing Parameters No Reference Description Min Max Units 1 tTCKmin TCK_RET period 40 1000 ns 2 tTCKhighmin TCK_RET high pulse duration 15 ns 3 tTCKlowmin TCK_RET low pulse duration 15 ns 4 td(XTMXmin) TMS/TDI valid from TCK_RET low (default timing) 6 12 ns td(XTMXmax) 5 td(XTMXmin) TMSFTDI valid from TCK_RET high (optional tim- ing) 6 12 ns td(XTMXmax) 6 tsu(XTDOmin) TDO setup time to TCK_RET high 6 ns 7 thd(XTDOmin) TDO hold time from TCK_RET high 4 ns 765 TDO TMS TDI (Optional) 4 1.5 V 2 TCK_RET TMS TDI (Default) 3 1 2.6 MPSD Emulator Pod Signal Timing Figure 2-5 shows the signal timings for the emulator. Table 4 defines the timing parameters for the emulator. The timing parameters are calculated from standard data sheet parts used in the emulator and cable pod. These parameters are for reference only. Spectrum Digital does not test or guarantee these timings. Figure 2-5. Emulator POD Timing Table 4: Emulator Pod Timing Parameters No. Reference Description Min Max Units 1 tH3min H3 period 40 200 ns tH3max 2 tH3highmin H3 high pulse duration 8 ns 3 tH3lowmin H3 low pulse duration 8 ns 4 td(EMU0,1,2) EMU0, 1, 2 valid from H3 low 6 12 ns 5 tsu(EMU3) EMU3 setup time to H3 high 6 ns 6 thd(EMU3) EMU3 hold time from H3 high 4 ns 65 4 EMU2 EMU1 EMU0 EMU3 1 H3 2 3 SEED International Ltd. 2-8 XDSUSB Emulator Pod Installation Guide