2级级联连接的

United States Patent [-191 Ushida et a1. Z-STAGE DIFFERENTIAL AMPLIFIER CONNECT ED IN CASCADE Susumu Ushida; Sadao Igarashi, both of Souma, Japan Alps Electric Co., Ltd., Tokyo, Japan [54] [75] Inventors: [73] [21] [22] Assignee: Appl. No.: 573,951 Filed: Aug. 28, 1990 [30] Foreign Application Priority Data Oct. 6, 1989 [JP] Japan ................................ .. 1-261477 [51] Int. Cl.5 ............................................. .. H03F 3/45 [52] US. Cl. ............................ .. 330/261; 330/310 [58] Field of Search ............. .. 330/252, 261, 296, 310; 358/184 References Cited U.S. PATENT DOCUMENTS 4,490,685 12/1984 Sano . FOREIGN PATENT DOCUMENTS [56] 5,057,788 Oct. 15, 1991 Patent Number: Date of Patent: [11] [45] Primary Examiner-Steven Mottola Attorney, Agent, or Firm—Guy W. Shoup; B. Noel Kivlin [57] ABSTRACT A two-stage differential ampli?er connected in cascade according to the present invention is suitable for fabri cation within an integrated circuit, in which a constant current source circuit is connected with the common emitters of the transistors in the preceding stage differ ential ampli?er, and the emitters of the transistors in the succeeding stage differential ampli?er are connected with the collectors of these transistors through impe dance elements. Current consumption in the overall ampli?er is reduced and heat production therein is sup pressed. Furthermore, since a capacitor is connected between the collector of each of the transistors in the preceding stage differential ampli?er and the base of each of the transistors in the succeeding stage differen tial ampli?er, it is possible to match easily the input and the output impedances in the succeeding and preceding ampli?er by means of this capacitor and the impedance elements described above, 0095824 12/1983 European Pat. Off. .......... .. 330/261 0123214 7/1983 Japan ................................. .. 330/261 1 Claim, 4 Drawing Sheets OUTPUT (VCC ) r-M? 7 3 US. Patent Oct. '15, 1991 Sheet 1 of 4 ' 5,057,788 H6. 7 OUTPUT (VCC ) PA“ 3 R2 \% (Vb 1) RA 5 Q3 II 'I INT’UT US. Patent Oct. 15, 1991 7 Sheet 2 of 4 ' 5,057,788 F|G.2AO M 0 FIGZB FIG. 2C F|G.2D MAL US. Patent Oct. 15, 1991 I Sheet 3 of4 ' 5,057,788 US. Patent Oct. ‘15, 1991 _ Sheet 4 of 4 - 5,057,788 F/G. 3 PR/UR ART (Vcc) 253T 7 3 1. § 3 (a fA/Ci 'l \NJC, 5,057,788 1 Z-STAGE DIFFERENTIAL AMPLIFIER CONNECTED IN CASCADE FIELD OF THE INVENTION The present invention relates to a 2-stage differential ampli?er connected in cascade suitable for high fre quency ampli?cation in a tuner, a modulator for TV/V TR, a CATV converter, or other apparatus. BACKGROUND OF THE INVENTION FIG. 3 is a circuit diagram showing the construction of a prior art differential ampli?er for high frequency ampli?cation used in a tuner for TV/V TR. In the ?g ure, transistors Q1 and Q2 constitute a differential am pli?er in the preceding stage, in which the bases of these transistors Q1 and Q2 are connected with input termi nals 1 and 2, respectively. A transistor Q3 and a resistor R5 constitute a constant current source circuit which is connected between the common emitters of the transis tors Q1 and Q2 and ground. Furthermore, resistors R1 and R2 are connected in series between a power supply terminal 7 and ground and a base bias voltage is sup plied from the connecting point of the resistors R1 and R2 to the transistor Q1. Similarly resistors R3 and R4 are connected in series between the power supply termi nal 7 and ground and a base bias voltage is supplied from the connecting point thereof to the transistor Q2. The collectors of the transistors Q1 and Q2 are con nected with the power supply terminal 7 through resis tors R6 and R9, respectively. Transistors Q4 and Q5 constitute a differential ampli ?er in the succeeding stage. The bases of transistors Q4 and Q5 are connected with the collectors of the transis tors Q1 and Q2, respectively. A transistor Q6 and a resistor R10 constitute a constant current source circuit which is connected between the common emitter of the transistors Q1 and Q2 and ground. The collectors of the transistors Q4 and Q5 are connected with the power supply terminal 7 through resistors R7 and R8, respec tively. As clearly seen from the connection relation de scribed above, the circuit constitutes a 2-stage differen tial ampli?er connected in cascade consisting of a pre ceding stage differential ampli?er comprising the tran sistors Q1, Q2 and Q3 and the resistors R1, R2, R3, R4, R6 and R9, whose inputs are the input terminals 1 and 2, the collectors of the transistors Q1 and Q2 serving as the outputs, and a succeeding stage differential ampli?er comprising the transistors Q4, Q5 and Q6 and the resis» tors R6, R7, R8, R9 and R10, whose inputs are the bases of the transistors Q4 and Q5, the collectors of the tran sistors Q4 and Q5 serving as the outputs. The operation of the circuit described above is next explained. At ?rst, when the power supply Vcc is switched on, voltages are obtained at the connecting point of the resistors R1 and R2 and the connecting point of the resistors R3 and R4, respectively, dividing the power supply voltage Vcc. These voltages are applied to the base of the transistor Q1 and the base of the transistor Q2, respectively. Further the voltage Vcc is applied to the collector of the transistor Q1 through the resistor R6 and to the collector of the transistor Q2 through the resistor R9. If characteristics of the transistors Q1 and Q2 are identical and the base bias voltages applied thereto are equal to each other, the emitter currents of the transistor Q1 and Q2 are also equal to each other, 45 55 65 2 the intensity of which is equal to g of the collector current of the transistor Q3. Since the transistor Q3 constitutes a constant current source circuit, the collec tor current thereof is constant and the intensity of this current is determined unequivocally by the voltage Vb1 (arbitrary constant voltage) applied to a terminal 5 and the resistance of the resistor R5. The voltage Vcc is applied to the bases of the transis tors Q4 and Q5 through the resistors R6 and R9, respec tively. If the resistances of the resistors R6 and R9 are equal to each other, the DC collector currents of the transistors Q1 and Q2 are equal to each other and there fore the voltage drops across the resistors R6 and R9 are equal to each other. Consequently, the base bias voltages of the transistors Q4 and Q5 are equal to each other and the magnitude thereof is a value obtained by subtracting the voltage drop across the resistor R6 or R9 from the voltage Vcc. Further, the voltage Vcc is applied to the collectors of the transistors Q4 and Q5 through the resistors R7 and R8. If the characteristics of the transistors Q4 and Q5 are identical, the emitter cur rents thereof are also equal to each other, the intensity of which is equal to % of the collector current of the transistor Q6. Since the transistor Q6 constitutes a con stant current source circuit the collector current thereof is constant and the intensity of this current is deter mined unequivocally by the voltage Vb2 (arbitrary constant voltage) applied to a terminal 6 and the resis tance of the resistor R10. In the DC operation state as described above, when a balanced high frequency signal is inputted in the termi nals 1 and 2, voltages having phases opposite to each other are applied to the bases of the transistors Q1 and Q2. As a result, when the base voltage of the transistor Q1 rises and the emitter current thereof increases, the base voltage of the transistor Q2 decreases and the emit ter current thereof decreases. If the base voltage of the I transistor Q2 rises and the emitter current thereof in creases, the base voltage of the transistor Q1 descends and the emitter current decreases. In accordance with the operations described above, since the sum of the emitter currents of the transistors Q1 and Q2 is kept constant by the action of the constant current source circuit composed of the transistor Q3, currents having a phase difference equal to 180° (opposite phase) and a same amplitude ?ow through the emitters of the transis tors Q1 and Q2. Consequently, the collector currents of the transistors Q1 and Q2 also have phases opposite to each other and therefore an ampli?ed balanced high frequency signal is outputted from the collectors of the transistors Q1 and Q2. The ampli?ed balanced high frequency signal is in putted from the collectors of the transistors Q1 and Q2 in the preceding stage differential ampli?er to the bases of the transistors Q4 and Q5. In this way, voltages hav ing phases opposite to each other are applied to the bases of the transistors Q4 and Q5. As a result, when the base voltage of the transistor Q4 rises and the emitter current thereof increases, the base voltage of the transis tor Q5 descends and the emitter current decreases. Since the sum of the emitter currents of the transistors Q4 and Q5 is kept constant by the action of the constant current source circuit composed of the transistor Q6, currents having a phase differential equal to 180° (oppo site phase) and a same amplitude ?ow through the emit ters of the transistors Q4 and Q5. Consequently, the collector currents of the transistor Q4 and Q5 also have 5,057,788 3 phases opposite to each other, and therefore an further ampli?ed balanced high frequency signal is outputted from the collectors of the transistors Q4 and Q5. The prior art circuit described above has drawbacks as described below. 1. Since a constant current source circuit is necessary for each of the stages of the differential ampli?er, the circuit is complicated. 2. Since working current ?ows separately through the preceding stage ampli?er and the succeeding stage ampli?er current consumption is great and the power supply must be large. Further, associated therewith, heat production is great. Furthermore, as a method for improving distortion characteristics of the ampli?er, it is necessary to in crease working current of the transistors and if such increase in the working current is realized, the problem of heat production becomes more signi?cant. In partic ular, in the case of ICs or LSIs, a problem takes place that heat is apt to be accumulated because of a high density integration and it is dif?cult to deal with pro duced heat. 3. Since the total current ?owing through the circuit is divided into two parts ?owing through the preceding and the succeeding ampli?er, unless the capacity of the power supply is considerably great, it is not possible to obtain any satisfactory working current optimizing the distortion characteristics of each of the ampli?ers. Con sequently the distortion characteristics are poor. OBJECT OF THE INVENTION The present invention has been done in view of the situation described above and the object thereof is to provide a Z-stage differential ampli?er connected in cascade having a simple circuit construction, good dis tortion characteristics, and capable of suppressing heat production. SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is characterized in that it comprises a ?rst and a second transistor constituting a preceding stage differ ential ampli?er, whose emitters are connected in com mon; a third and a fourth transistor constituting a suc ceeding stage differential ampli?er, whose emitters are connected in common; a ?rst capacitor connected be tween the collector of the ?rst transistor and the base of the third transistor; a second capacitor connected be tween the collector of the second transistor and the base of the fourth transistor; a constant current source circuit connected between the common emitter of the ?rst and the second transistor and the ground; and a ?rst and a second impedance circuit connected in series between the collectors of the ?rst and the second transistor, the common emitter of the third and the fourth transistor being connected with the connecting point of the ?rst and the second impedance circuit. The construction described above gives rise to a ?rst current path consisting of the third transistor, the ?rst transistor and the constant current source circuit, and a second current path consisting of the fourth transistor, the second transistor and the constant current source circuit. In this way, by equalizing the characteristics and the working conditions of the corresponding tran sistors, it is possible to equalize the intensities of the currents ?owing through the current paths to each other. Therefore, the balanced high frequency signal inputted in the preceding amplifying circuit is ampli?ed 30 35 40 45 50 55 60 65 4 successively by the preceding and the succeeding stage amplifying circuit without destroying the balanced rela tion. Furthermore, since currents having phases opposite to each other flow through the emitters of the third and the fourth transistors, AC components thereof compen sate each other. As a result, the connecting point of the emitters, i.e., the connecting point of the ?rst and the second impedance circuits, is equivalently grounded in view of the high frequency. Consequently the collec tors of the ?rst and the second transistor are grounded in view of the high frequency through the ?rst and the second impedance circuits. In this way, an ampli?ed balanced high.frequency signal is obtained at the collec tors of the ?rst and the second transistor. and this bal anced high frequency signal is supplied to the bases of the third and the fourth transistor through the ?rst and the second capacitors. That is, the preceding and the succeeding amplifying circuit are coupled by the ?rst and the second capacitors and the ?rst and the second impedance circuits. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing the construction of an embodiment of the present invention; FIGS. 2A, 2N, 2C, 2D, E, 2F, 26, and 2H are circuit diagrams showing concrete examples of the impedance circuits Z1 and Z2 in the embodiment indicated in FIG. 1; and FIG. 3 is a circuit diagram showing the construction of a prior art circuit. DETAILED DESCRIPTION I-Iereinbelow, an embodiment of the present inven tion will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing the construction of the embodiment of the present invention. The parts corresponding to those indicated in FIG. 3 explained previously are denoted by the same reference numerals and explanation thereof is omitted. This embodiment differs from the prior art circuit described previously at several points as indicated be low. A ?rst point is that resistors R13 and R14 are inserted between the resistor R1 and the power supply terminal 7 and between the resistor R3 and the power supply terminal 7, respectively. By means thereof, the voltage Vcc is divided by the resistors R2, R1 and R13, and voltages thus obtained are applied to the bases of the transistors Q1 and Q4, acting as bias voltages. Similarly, voltages obtained by dividing the voltage Vcc by the resistors R4, R3 and R14 act as base bias voltages for the transistors Q2 and Q5. Another point is that a coupling capacitor C1 is in serted between the collector of the transistor Q1 and the base of the transistor Q4, while a coupling capacitor C2 is inserted between the collector of the transistor Q2 and the base of the transistor Q5. Furthermore, impe dance circuits Z1 and Z2 are inserted in series between the collectors of the transistors Q1 and Q2 and the con necting point of these impedance circuits Z1 and Z2 is connected with the common emitter of the transistors Q4 and Q5. The impedance circuits Z1 and Z2 are DC passing type circuits having characteristics identical to each other. Representative examples are indicated in FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 26, and 2H, in which R represents a resistor; C a capacitor; L a coil, and l a distributed constant line. 5,057,788 5 These are the different points between the present embodiment and the prior art circuit. It can be under stood that the present embodiment is roughly composed of the preceding stage differential ampli?er consisting of the transistors Q1, Q2 and Q3 and the resistors R1, R2, R3, R4, R13 and R14 (whose inputs are the input terminals 1 and 2, the outputs thereof being the collec tors of the transistors Q1 and Q2), the succeeding stage differential ampli?er consisting of the transistors Q4 and Q5 and the resistors R1, R2, R3, R4, R7, R8, R13 and R14 (whose inputs are the bases of the transistors Q4 and Q5, the outputs thereof being the collectors of the same transistors), and a coupling circuit consisting of the coupling capacitors C1 and C2 and the impedance circuits Z1 and Z2 inserted between the output termi nals of the preceding differential ampli?er and the input terminals of the succeeding differential ampli?er. The overall circuit is a differential ampli?er. The operation of the embodiment using the construc tion described above will next be explained. The working current of each of the transistors is ?rst explained. If the resistances of the resistors R1, R2 and R13 as well as the resistors R3, R4 and R14 are so determined that the base bias voltage of the transistors Q4 and Q5 and the base bias voltage of the transistors Q1 and Q5 are identical to each other, all the base currents ?owing through the transistors Q1, Q2, Q4 and Q5 have a same intensity. Here there are two paths of currents to be considered, i.e. a ?rst path of resistor R7 —~> transistor Q4 —» impedance circuit Z1 —> transistor Q1 —> transis tor Q3 and a second path of resistor R8 —> transistor Q5 —> impedance circuit Z2 —> transistor Q2 ——> transistor Q3. If the characteristics of the transistors Q1 and Q2 as well as those of the transistors Q4 and Q5 are identical to each other, since the transistor Q3 constitutes a con stant current source circuit, the intensity of the current flowing through the ?rst path and that ?owing through the second path are equal to each other, which is equal to g of the collector current of the transistor Q3. In the DC operation state described above, when the balanced high frequency signal is inputted in the termi nals 1 and 2, voltages having phases opposite to each other are applied to the bases of the transistors Q1 and Q2 in the preceding stage differential ampli?er. Conse quently, when the base voltage of the transistor Q1 rises and .the emitter current thereof increases, the base volt age of the transistor Q2 descends and the emitter cur rent thereof decreases. When the base voltage of the transistor Q2 rises and the emitter current increases, the base voltage of the transistor Q1 descends and the emit ter current decreases. Since the sum of the emitter currents of the transis tors Q1 and Q2 is kept constant due to the action of the constant current source circuit using the transistor Q3, currents having a phase difference of 180° (phases oppo site to each other) and a same current amplitude flow through the emitters of the transistors Q1 and Q2. Con sequently the collector currents of the transistors Q1 and Q2 have phases opposite to each other. An ampli fled balanced high frequency signal is taken out from the collectors of transistors Q1 and Q2. The balanced high frequency signal ampli?ed by the preceding stage differential ampli?er is inputted in the bases of the transistors Q4 and Q5 in the succeeding stage differential ampli?er through the couplin