sinwt 频率可调U1 AD9854ASQ手册 输出sinx

REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9854 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 CMOS 300 MHz Quadrature Complete-DDS FUNCTIONAL BLOCK DIAGRAM AD9854 DIGITAL MULTIPLIERS SYSTEM CLOCK 12-BIT CONTROL DAC DATA DAC RSET PHASE/OFFSET MODULATION INV. SINC FILTER PH A SE A CC UM UL AT O R FR EQ UE NC Y A CC UM UL AT O R 14-BIT PHASE OFFSET/ MODULATION 48-BIT FREQUENCY TUNING WORD FREQUENCY TUNING WORD/PHASE WORD MULTIPLEXER AND RAMP START STOP LOGIC PROGRAMMABLE RATE AND UPDATE CLOCKS COMPARATOR PROGRAMMING REGISTERS 43–203 REF CLK MULTI- PLEXER DIFF/SINGLE SELECT REFERENCE CLOCK IN FSK/BPSK/HOLD DATA IN BIDIRECTIONAL I/O UPDATE READ WRITE SERIAL/PARALLEL SELECT 6-BIT ADDRESS OR SERIAL PROGRAMMING LINES 8-BIT PARALLEL LOAD MASTER RESET +VS GND CLOCK OUT ANALOG IN SHAPED ON/OFF KEYING ANALOG OUT ANALOG OUT 300MHz DDS I/O PORT BUFFERS 12-BIT AM MOD RAMP-UP/-DOWN CLOCK/LOGIC AND MULTIPLEXER SI NE -T O -A M PL IT UD E CO NV ER TE R I Q INV. SINC FILTER 12-BIT "Q" OR CONTROL DAC MUX 12-BIT "I" DAC FEATURES 300 MHz Internal Clock Rate Integrated 12-Bit Output DAC Ultrahigh-Speed, 3 ps RMS Jitter Comparator Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz (61 MHz) AOUT 43 to 203 Programmable Reference Clock Multiplier Dual 48-Bit Programmable Frequency Registers Dual 14-Bit Programmable Phase Offset Registers 12-Bit Amplitude Modulation and Programmable Shaped On/Off Keying Function Single Pin FSK and PSK Data Interface Linear or Nonlinear FM Chirp Functions with Single Pin Frequency “Hold” Function Frequency-Ramped FSK <25 ps RMS Total Jitter in Clock Generator Mode Automatic Bidirectional Frequency Sweeping SIN(x)/x Correction Simplified Control Interface 10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or 100 MHz Parallel 8-Bit Programming 3.3 V Single Supply Multiple Power-Down Functions Single-Ended or Differential Input Reference Clock Small 80-Lead LQFP Packaging APPLICATIONS Agile, Quadrature L.O. Frequency Synthesis Programmable Clock Generator FM Chirp Source for Radar and Scanning Systems Test and Measurement Equipment Commercial and Amateur RF Exciter GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high-speed, high-performance quadrature D/A converters and a comparator to form a digitally-programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase-amplitude- programmable sine and cosine outputs that can be used as an agile L.O. in communications, radar, and many other applications. The AD9854’s innovative high-speed DDS core provides 48-bit frequency resolution (1 microHertz tuning steps). Phase trunca- tion to 17 bits assures excellent SFDR. The AD9854’s circuit (continued on page 14) –2– REV. 0 AD9854–SPECIFICATIONS (VS = 3.3 V 6 5%, RSET = 3.9 kV external reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 103 for AD9854ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 103 for AD9854AST unless otherwise noted.) Test AD9854ASQ AD9854AST Parameter Temp Level Min Typ Max Min Typ Max Unit REF CLOCK INPUT CHARACTERISTICS1 Internal Clock Frequency Range FULL VI 5 300 5 200 MHz External REF Clock Frequency Range REFCLK Multiplier Enabled FULL VI 5 75 5 50 MHz REFCLK Multiplier Disabled FULL VI 5 300 5 200 MHz Duty Cycle 25 ° C IV 45 50 55 45 50 55 % Input Capacitance 25 ° C IV 3 3 pF Input Impedance 25 ° C IV 100 100 k W Differential Mode Common-Mode Voltage Range Minimum Signal Amplitude 25 ° C IV 800 800 mV p-p Common-Mode Range 25 ° C IV 1.6 1.75 1.9 1.6 1.75 1.9 V VIH (Single-Ended Mode) 25 ° C IV 2.3 2.3 V VIL (Single-Ended Mode) 25 ° C IV 1 1 V DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed FULL I 300 200 MSPS Resolution 25 ° C IV 12 12 Bits I and Q Full-Scale Output Current 25 ° C IV 5 10 20 5 10 20 mA I and Q DAC DC Gain Imbalance2 25 ° C I –0.5 +0.15 +0.5 –0.5 +0.15 +0.5 dB Gain Error 25 ° C I –6 +2.25 –6 +2.25 % FS Output Offset 25 ° C I 2 2 m A Differential Nonlinearity 25 ° C I 0.3 1.25 0.3 1.25 LSB Integral Nonlinearity 25 ° C I 0.6 1.66 0.6 1.66 LSB Output Impedance 25 ° C IV 100 100 k W Voltage Compliance Range 25 ° C I –0.5 +1.0 –0.5 +1.0 V DAC DYNAMIC OUTPUT CHARACTERISTICS I and Q DAC Quad. Phase Error 25 ° C IV 0.2 1 0.2 1 Degrees DAC Wideband SFDR 1 MHz to 20 MHz AOUT 25 ° C V 58 58 dBc 20 MHz to 40 MHz AOUT 25 ° C V 56 56 dBc 40 MHz to 60 MHz AOUT 25 ° C V 52 52 dBc 60 MHz to 80 MHz AOUT 25 ° C V 48 48 dBc 80 MHz to 100 MHz AOUT 25 ° C V 48 48 dBc 100 MHz to 120 MHz AOUT 25 ° C V 48 dBc DAC Narrowband SFDR 10 MHz AOUT ( – 1 MHz) 25 ° C V 83 83 dBc 10 MHz AOUT (– 250 kHz) 25 ° C V 83 83 dBc 10 MHz AOUT ( – 50 kHz) 25 ° C V 91 91 dBc 41 MHz AOUT ( – 1 MHz) 25 ° C V 82 82 dBc 41 MHz AOUT (– 250 kHz) 25 ° C V 84 84 dBc 41 MHz AOUT ( – 50 kHz) 25 ° C V 89 89 dBc 119 MHz AOUT (– 1 MHz) 25 ° C V 71 dBc 119 MHz AOUT (– 250 kHz) 25 ° C V 77 dBc 119 MHz AOUT (– 50 kHz) 25 ° C V 83 dBc Residual Phase Noise (AOUT = 5 MHz, Ext. CLK = 30 MHz, REFCLK Multiplier Engaged at 10 · ) 1 kHz Offset 25 ° C V 140 140 dBc/Hz 10 kHz Offset 25 ° C V 138 138 dBc/Hz 100 kHz Offset 25 ° C V 142 142 dBc/Hz (AOUT = 5 MHz, Ext. CLK = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 25 ° C V 142 142 dBc/Hz 10 kHz Offset 25 ° C V 148 148 dBc/Hz 100 kHz Offset 25 ° C V 152 152 dBc/Hz Pipeline Delays Phase Accumulator and DDS Core 25 ° C IV 17 17 SysClk Cycles Inverse Sinc Filter 25 ° C IV 12 12 SysClk Cycles Digital Multiplier 25 ° C IV 10 10 SysClk Cycles –3–REV. 0 AD9854 Test AD9854ASQ AD9854AST Parameter Temp Level Min Typ Max Min Typ Max Unit MASTER RESET DURATION 25 ° C IV 10 10 SysClk Cycles COMPARATOR INPUT CHARACTERISTICS Input Capacitance 25 ° C V 3 3 pF Input Resistance 25 ° C IV 500 500 k W Input Current 25 ° C I – 1 – 5 – 1 – 5 m A Hysteresis 25 ° C IV 10 20 10 20 mV p-p COMPARATOR OUTPUT CHARACTERISTICS Logic “1” Voltage, High Z Load FULL VI 3.1 3.1 V Logic “0” Voltage, High Z Load FULL VI 0.16 0.16 V Output Power, 50 W Load, 120 MHz Toggle Rate 25 ° C I 9 11 9 11 dBm Propagation Delay 25 ° C IV 3 3 ns Output Duty Cycle Error3 25 ° C I –10 – 1 +10 –10 – 1 +10 % Rise/Fall Time, 5 pF Load 25 ° C V 2 2 ns Toggle Rate, High Z Load 25 ° C IV 300 350 300 350 MHz Toggle Rate, 50 W Load 25 ° C IV 375 400 375 400 MHz Output Cycle-to-Cycle Jitter4 25 ° C IV 4.0 4.0 ps rms COMPARATOR NARROWBAND SFDR4 10 MHz (– 1 MHz) 25 ° C V 84 84 dBc 10 MHz (– 250 kHz) 25 ° C V 84 84 dBc 10 MHz (– 50 kHz) 25 ° C V 92 92 dBc 41 MHz (– 1 MHz) 25 ° C V 76 76 dBc 41 MHz (– 250 kHz) 25 ° C V 82 82 dBc 41 MHz (– 50 kHz) 25 ° C V 89 89 dBc 119 MHz (– 1 MHz) 25 ° C V 73 73 dBc 119 MHz (– 250 kHz) 25 ° C V 73 73 dBc 119 MHz (– 50 kHz) 25 ° C V 83 83 dBc CLOCK GENERATOR OUTPUT JITTER5 5 MHz AOUT 25 ° C V 23 23 ps rms 40 MHz AOUT 25 ° C V 12 12 ps rms 100 MHz AOUT 25 ° C V 7 7 ps rms PARALLEL I/O TIMING CHARACTERISTICS TASU (Address Setup Time to WR Signal Active) FULL IV 8.2 7.8 8.2 7.8 ns TADHW (Address Hold Time to WR Signal Inactive) FULL IV 0 0 ns TDSU (Data Setup Time to WR Signal Inactive) FULL IV 2.1 1.6 2.1 1.6 ns TDHD (Data Hold Time to WR Signal Inactive) FULL IV 0 0 ns TWRLOW (WR Signal Minimum Low Time) FULL IV 2.2 1.8 2.2 1.8 ns TWRHIGH (WR Signal Minimum High Time) FULL IV 7 7 ns TWR (WR Signal Minimum Period) FULL IV 10 10 ns TADV (Address to Data Valid Time) FULL V 15 15 15 15 ns TADHR (Address Hold Time to RD Signal Inactive) FULL IV 5 5 ns TRDLOV (RD Low-to-Output Valid) FULL IV 15 15 ns TRDHOZ (RD High-to-Data Three-State) FULL IV 10 10 ns SERIAL I/O TIMING CHARACTERISTICS TPRE (CS Setup Time) FULL IV 30 30 ns TSCLK (Period of Serial Data Clock) FULL IV 100 100 ns TDSU (Serial Data Setup Time) FULL IV 30 30 ns TSCLKPWH (Serial Data Clock Pulsewidth High) FULL IV 40 40 ns TSCLKPWL (Serial Data Clock Pulsewidth Low) FULL IV 40 40 ns TDHLD (Serial Data Hold Time) FULL IV 0 0 ns TDV (Data Valid Time) FULL V 30 30 ns CMOS LOGIC INPUTS Logic “1” Voltage 25 ° C I 2.7 2.7 V Logic “0” Voltage 25 ° C I 0.4 0.4 V Logic “1” Current 25 ° C IV – 5 – 12 m A Logic “0” Current 25 ° C IV – 5 – 12 m A Input Capacitance 25 ° C V 3 3 pF –4– REV. 0 AD9854–SPECIFICATIONS CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9854 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE Test AD9854ASQ AD9854AST Parameter Temp Level Min Typ Max Min Typ Max Unit POWER SUPPLY6 +VS Current7 25 ° C I 1050 1210 755 865 mA +VS Current8 25 ° C I 710 816 515 585 mA +VS Current9 25 ° C I 600 685 435 495 mA PDISS7 25 ° C I 3.475 4.190 2.490 3.000 W PDISS8 25 ° C I 2.345 2.825 1.700 2.025 W PDISS9 25 ° C I 1.975 2.375 1.435 1.715 W PDISS Power-Down Mode 25 ° C I 1 50 1 50 mW NOTES 1The reference clock inputs are configured to accept a 1 V p-p (minimum) dc offset sine wave centered at one-half the applied V DD or a 3 V TTL-level pulse input. 2The I and Q gain imbalance is digitally adjustable to less than 0.01 dB. 3Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold. 4Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075. 5Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 W . 6Simultaneous operation at the maximum ambient temperature of 85 ° C and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz for the thermally-enhanced 80-lead LQFP may cause the maximum die junction temperature of 150 ° C to be exceeded. Refer to the section titled Power Dissipation and Thermal Considerations for derating and thermal management information. 7All functions engaged. 8All functions except inverse sinc engaged. 9All functions except inverse sinc and digital multipliers engaged. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I – 100% Production Tested. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – Devices are 100% production tested at 25 ° C and guaranteed by design and characterization testing for industrial operating temperature range. ABSOLUTE MAXIMUM RATINGS* Maximum Junction Temperature . . . . . . . . . . . . . . . . 150 ° C VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . –65 ° C to +150° C Operating Temperature . . . . . . . . . . . . . . . . . –40° C to +85° C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300 ° C Maximum Clock Frequency . . . . . . . . . . . . . . . . . . 300 MHz *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9854ASQ –40 ° C to +85° C Thermally-Enhanced 80-Lead LQFP SQ-80 AD9854AST –40 ° C to +85° C 80-Lead LQFP ST-80 AD9854/PCB 0 ° C to 70 ° C Evaluation Board AD9854 –5–REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Pin Name Function 1–8 D7–D0 Eight-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode. 9, 10, 23, DVDD Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND 24, 25, 73, and DGND. 74, 79, 80 11, 12, 26, DGND Connections for Digital Circuitry Ground Return. Same potential as AGND. 27, 28, 72, 75, 76, 77, 78 13, 35, 57, NC No Internal Connection. 58, 63 14–19 A5–A0 Six-Bit Parallel Address Inputs for Program Registers. Used only in parallel programming mode. A0, A1, and A2 have a second function when the serial programming mode is selected. See immediately below. (17) A2/IO RESET Allows a RESET of the serial communications bus that is unresponsive due to improper program- ming protocol. Resetting the serial bus in this manner does not affect previous programming nor does it invoke the “default” programming values seen in the Table V. Active HIGH. (18) A1/SDO Unidirectional Serial Data Output for Use in 3-Wire Serial Communication Mode. (19) A0/SDIO Bidirectional Serial Data Input/Output for Use in 2-Wire Serial Communication Mode. 20 I/O UD Bidirectional Frequency Update Signal. Direction is selected in control register. If selected as an input, a rising edge will transfer the contents of the programming registers to the internal works of the IC for processing. If I/O UD is selected as an output, an output pulse (low to high) of eight system clock cycle duration indicates that an internal frequency update has occurred. 21 WRB/SCLK Write Parallel Data to Programming Registers. Shared function with SCLK. Serial clock signal associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with WRB when the parallel mode is selected. 22 RDB/CSB Read Parallel Data from Programming Registers. Shared function with CSB. Chip-select signal associated with the serial programming bus. Active LOW. This pin is shared with RDB when the parallel mode is selected. 29 FSK/BPSK/ Multifunction Pin According to the Mode of Operation Selected in the Programming Control Register. HOLD If in the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects Phase 1, logic high selects Phase 2. If in the Chirp mode, logic high engages the HOLD function causing the frequency accumulator to halt at its current location. To resume or commence Chirp, logic low is asserted. 30 SHAPED Must First Be Selected in the Programming Control Register to Function. A logic high will cause the KEYING I and Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate. Logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate. 31, 32, 37, AVDD Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND 38, 44, 50, and DGND 54, 60, 65 33, 34, 39, AGND Connections for Analog Circuitry Ground Return. Same potential as DGND. 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 36 VOUT Internal High-Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50 W load as well as standard CMOS logic levels. 42 VINP Voltage Input Positive. The internal high-speed comparator’s noninverting input. 43 VINN Voltage Input Negative. The internal high-speed comparator’s inverting input. 48 IOUT1 Unipolar Current Output of the I or Cosine DAC. 49 IOUT1B Complementary Unipolar Current Output of the I or Cosine DAC. 51 IOUT2B Complementary Unipolar Current Output of the Q or Sine or DAC. 52 IOUT2 Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept external 12-bit data in lieu of internal sine data. This allows the AD9854 to emulate the AD9852 control DAC function. AD9854 –6– REV. 0 Pin No. Pin Name Function 55 DACBP Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 m F chip cap from this pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR degradation). 56 DAC RSET Common Connection for Both I and Q DACs to Set the Full-Scale Output Current. RSET = 39.9/IOUT. Normal RSET range is from 8 k W (5 mA) to 2 kW (20 mA). 61 PLL FILTER This pin provides the connection for the external zero compensation network of the REFCLK Multiplier’s PLL loop filter. The zero compensation network consists of a 1.3 kW resistor in series with a 0.01 m F capacitor. The other side of the network should be connected to AVDD as close as possible to Pin 60. For optimum phase noise performance, the REFCLK Multiplier can be bypassed by setting the “Bypass PLL” bit in control register 1E. 64 DIFF CLK Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK ENABLE and REFCLKB (Pins 69 and 68 respectively). The minimum differential signal amplitude required is 800 mV p-p. The centerpoint or common-mode range of the differential signal ranges from 1.6 V to 1.9 V. 68 REFCLKB The Complementary (180 Degrees Out-of-Phase) Differential Clock Signal. User should tie this pin high or low when single-ended clock mode is selected. Same signal levels as REFCLK. 69 REFCLK Single-Ended Reference Clock Input or One of Two Differential Clock Signals. Normal 3.3 V CMOS logic levels or 1 V p-p sine wave centered about 1.6 V. 70 S/P SELECT Selects Between Serial Programming Mode (Logic LOW) and Parallel Programming Mode (Logic High). 71 MASTER Initializes the serial/parallel programming bus to prepare for user programming; sets programming RESET registers to a “do-nothing” state defined by the default values seen in the Table V. Active on logic high. Asserting MASTER RESET is essential for proper operation upon power-up. AD9854 –7–REV. 0 PIN CONFIGURATION PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD9854 80-LEAD LQFP 14 3 14 3 1.4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 4020 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D7 D6 D5 D4 D3 D2 D1 D0 DVDD DVDD DGND DGND NC A5 A4 A3 A2/IO RESET A1/SDO A0/SDIO I/O UD W R B /S CL K R D B /C SB D VD D D VD D D VD D D G ND D G ND D G ND FS K/ BP SK /H O LD SH AP ED K EY IN G A VD D A VD D A G ND A G ND NC VO UT A VD D A VD D A G ND A G ND AGND VINP VINN AVDD AGND AGND AGND IOUT1 IOUT1B AVDD IOUT2B IOUT2 AGND AVDD DACBP DAC RSET NC NC AGND AVDD PL L FI LT ER A G ND N C D IF F CL K EN AB LE A VD D A G ND A G ND R EF CL O CK B R EF CL O CK S/ P SE LE CT M A ST ER R ES ET D G ND D VD D D VD D D G ND D G ND D G ND D G ND D VD D D VD D NC = NO CONNECT Figure 1. Equivalent Input and Output Circuits a. DAC Outputs b. Comparator Output c. Comparator Input d. Digital Input VDD IOUT IOUTB DIGITAL OUT VDD VDD VINP/ VINN VDD DIGITAL IN AD9854 –8– REV. 0 Figures 2–7 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz Fundamental Output, Reference Clock = 30 MHz, REFCLK Multiplier = 10. Each graph plotted from 0 MHz to 150 MHz. 0 START 0Hz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 15MHz/ STOP 150MHz Figure 2. Wideband SFDR, 19.1 MHz 0 START 0Hz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 15MHz/ STOP 150MHz Figure 3. Wideband SFDR, 39.1