Designing_with_Quartus_II_For_CPLDs_Ver7

nullDesigning with Quartus II Software for CPLDsDesigning with Quartus II Software for CPLDsIntroduction to Altera & Altera DevicesThe Programmable Solutions Company®The Programmable Solutions Company®Intellectual property (IP) Signal processing Communications Embedded processors Nios® IIDevices (continued) Stratix Cyclone Stratix GX MAX 7000/3000Tools Quartus II software SOPC Builder DSP Builder Nios II IDEDevices Stratix® II Cyclone™ II Stratix II GX MAX® IIProgrammable Logic FamiliesProgrammable Logic FamiliesStructured ASIC HardCopy® II, HardCopy Stratix High & medium density FPGAs Stratix II, Stratix, APEX™ II, APEX 20K, & FLEX 10K® Low-cost FPGAs Cyclone II & Cyclone FPGAs with clock data recovery Stratix II GX & Mercury™ CPLDs MAX II, MAX 7000 & MAX 3000 Embedded processor solutions Nios II, Excalibur™ Configuration devices Serial (EPCS) & enhanced (EPC)Software & Development ToolsSoftware & Development ToolsQuartus II Stratix II, Stratix, Stratix II GX, Stratix GX, Cyclone II, Cyclone. HardCopy II & HardCopy Stratix Devices APEX II, APEX 20K/E/C, Excalibur, & Mercury FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices MAX II, MAX 7000S/AE/B, MAX 3000A Devices Quartus II Web Edition Free version Not all features & devices included Targets all MAX II devices See www.altera.com for comparison MAX+PLUS® II All FLEX, ACEX, & MAX devicesDesigning with Quartus II Software for CPLDsDesigning with Quartus II Software for CPLDsMAX II OverviewMAX II Device Family OverviewMAX II Device Family OverviewDevice characteristics Non-volatile, instant-on programmable logic TSMC 0.18-μm, 6-lm flash process 240 to 2,210 logic elements (LEs) 80 to 272 user I/O pins Key benefits Lowest cost per I/O pin Low power consumption Fast performance High-densityMAX II Device FamilyMAX II Device Family(1) One macrocell is equivalent to approximately 1.3 logic elementsMAX II PerformanceMAX II PerformanceDelay for Worst-Case I/O Placement: (Full Diagonal Path Across Device)Delay for Best-Case I/O PlacementMAX II Packaging & User I/O PinsMAX II Packaging & User I/O PinsDenotes Vertical MigrationNotes: 1. TQFP: thin quad flat pack 2. FineLine BGA® package (1.0-mm pitch)MAX II is not pin compatible with previous MAX familiesAdditional Packaging FeaturesAdditional Packaging FeaturesIndustrial & automotive temperature grade support Lead-free packagingDevice AvailabilityDevice AvailabilityAll devices including lead free, industrial grade & extended temperature grade area available now!Designing with Quartus II Software for CPLDsDesigning with Quartus II Software for CPLDsMAX II ArchitectureMAX II ArchitectureMAX II ArchitectureLogic array I/O features Configuration Configuration flash memory (CFM) User flash memory (UFM) MAX II Architecture MAX II Architecture Staggered I/O PadsUser Flash MemoryLogic Elements (LEs)JTAG & Control CircuitryConfiguration Flash MemoryMAX II – How Does it Work?MAX II – How Does it Work?LEs comprised of SRAM-based elements built with flash process technology FPGA SRAM elements built on CMOS only Configuration flash memory block stores logic array’s SRAM configuration data Downloads upon sufficient VCC & enters user mode in 200-450 μs “Instant on” Small partition of flash memory block designed for user data storage called user flash memory (UFM block)MAX II is a single die with flash memory & logic array all built with flash process technologyMAX II Logic Array Blocks (LABs)MAX II Logic Array Blocks (LABs)10 Logic Elements (LEs) Identical to Cyclone & Stratix LEs Local interconnect 10 available LAB-wide control signals26 LAB Input Lines10 LE Feedback LinesLE Normal ModeLE Normal Modedata1addnsubdata2data34-Input LUTcindata4Register ChainRegsloadsclearaloadRow, Column & Direct Link RoutingLocal RoutingLUT ChainRegister Chainclock ena aclr DEV_CLRnLE Dynamic Arithmetic ModeLE Dynamic Arithmetic ModeSync Load & Clear LogicRegTwo 2-Input LUTs (Carry)Register Control SignalsRegister Chain InputData1Data2Data3Row, Column & Direct Link RoutingLocal RoutingTwo 2-Input LUTs (Sum)Register Chain OutputaddnsubCarry-Out LogicCarry-in LogicLAB Carry-in Carry-In0 Carry-In1Carry- Out1Carry- Out0Carry ChainsCarry ChainsLE1Sum1LE2Sum2LE4Sum4LE5Sum5LE3Sum3LAB Carry-In01A1 B2A2 B2A3 B3A4 B4A5 B5LE6Sum6LE7Sum7LE9Sum9LE10Sum10LE8Sum801A6 B6A7 B7A8 B8A9 B9A10 B10LAB Carry-OutLUTLUTLUTLUTSumCarry- Out0Carry- Out0LAB Carry-InCarry-In0 Carry-In1Data1 Data2LAB Carry Chain ConnectionsLAB Carry Chain ConnectionsCarry chain runs horizontal LE10 carries into LE1 of next LAB Carry chains end at row edge Do not extend across multiple rowsLAB RowLUT & Register ChainsLUT & Register ChainsLUT chain Output of LUT connects directly to LUT below Faster wide fan-in functions saving interconnect Register chain Output of register connects directly to register below LUT can be used for unrelated function (e.g., LE shift register) Both chains end at LAB boundaryTo LE3To LE3LUTRegLUTLE Chain Register ChainRegRegister Packing & FeedbackRegister Packing & FeedbackRegister packing LUT & register drive different outputs Normal mode only Ex. state machines Register feedback Register output feeds its own LUT Useful for registering device input signalsLELUTLELUTRegister PackingRegister FeedbackMultiTrack™ Interconnects (Routing)MultiTrack™ Interconnects (Routing)Horizontal interconnects DirectLink R4 Vertical interconnects Carry, LUT, register chains C4DirectLinkDirectLinkLABs/UFM directly drive into local interconnects of neighboring LABs/UFM in same row R4/C4 InterconnectsR4/C4 InterconnectsEach block has own R4/C4 resources to drive in all directions Each 4 labs in length Staggered interconnects End-to-end connections for longer routes LAB-neighboring LABs can use interconnects from neighboring labs Proximity is key to logic performance in MAX IIR4 InterconnectR4 InterconnectC4 InterconnectC4 InterconnectGlobal Clock NetworkGlobal Clock Network4 global clocks signals Any high fan-out signal can be used on global clock routing Register control signals: clock, OE, clear, preset, clock enable Protocol control signals: TRDY & IRDY for PCI Feeding logic LAB clock & LAB clear signals fed directly Other control signals use local interconnect to access LAB & I/OGlobal Clock SourcesGlobal Clock Sources4 dual purpose global clock pins GCLK[3..0] 2 on left side & 2 on right side Can be used as regular I/O pins Any LE or I/O pin can route to global network Global clock buffered to lab column clocks GCLK0Logic array GCLK1GCLK2GCLK344Global clock networkLAB Column Clocks[3..0]LAB Column Clocks[3..0]LAB Column Clocks[3..0]LAB Column Clocks[3..0]LAB Column ClocksLAB Column Clocks UFM BlockI/O RegionLAB Column Clocks[3..0]I/O RegionI/O RegionGlobal Clock Network4444444Notes:: Quartus II will automatically power down any unused column clocks. MAX II I/O ElementMAX II I/O Elementto/from CoreVCCIODtProgrammable Pull-Up ResistorBus-Hold CircuitVCCIOPCI Clamp Diode (1)Optional Schmitt TriggerFast I/OLE InputRow or ColumnOENotes: Available only in EPM1270 & EPM2210 DEV_OEMAX II Row I/O Block InterfaceNotes: Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and one data_in inputMAX II Row I/O Block InterfaceMAX II Column I/O Block InterfaceMAX II Column I/O Block InterfaceMAX II IOE FeaturesMAX II IOE FeaturesThere are no IOE registers in MAX II devices Small IOE provides low cost per I/O Features shared with MAX 7000B Programmable pull-up resistor Bus hold Open-drain output Programmable ground Hot-socketingMAX II IOE FeaturesMAX II IOE FeaturesUnique OE per pin Improvement over MAX 7000/3000 OE limitations LVTTL, LVCMOS & PCI support New & improved noise control features Schmitt trigger, slow slew, drive strength Dual-purpose device-wide control pins Output enable (DEV_OE) Clear (DEV_CLRn) Available as user I/O if disabledMAX II IOE Noise Control FeaturesMAX II IOE Noise Control FeaturesOptional Schmitt trigger available on every I/O for 3.3-V or 2.5-V VCCIO Provides hysteresis & noise immunity for slow rising inputs Input delay adder when used ~300 psTo Logic ArrayMAX II IOE Noise Control FeaturesMAX II IOE Noise Control FeaturesSlow slew rate option more aggressive than MAX 7K 5X slower edge rate between slow vs fast Affects both rising & falling edges Slow edge leads to large push-out ~8ns for 3.3-V LVTTL Programmable drive strength Two settings per I/O standard Maximum setting lower than MAX 7KAE Provides mechanism for controlling overshoot on board signals Reduces slew without large push-out penalty Optional Bus Hold CircuitryOptional Bus Hold CircuitryImproves signal integrity Holds signal in last driven state No need for external pull-up or pull-down resistors when the bus is tri-stated Individually selectable per I/O pinI/O Bank SegmentationI/O Bank SegmentationEPM240 & EPM570Bank 1Bank 2EPM1270 & EPM2210LVTTL LVCMOSLVTTL LVCMOSLVTTL LVCMOSLVTTL LVCMOSLVTTL LVCMOS PCILVTTL LVCMOSMAX II DeviceMAX II DeviceLVTTL: 3.3, 2.5 & 1.8 V LVCMOS: 3.3, 2.5, 1.8 & 1.5 V PCI: 3.3 V5-V Tolerance 5-V Tolerance MAX II inputs do not intrinsically tolerate 5-V signals 5-V tolerant input buffer requires too much die space Use external series resistor (R2) Enable PCI clamping diode Only available in I/O bank 3 of EPM1270 & EPM2210 devices Use external diode if EPM240 or EPM570 device is usedVCCIO 3.3V5.0V  0.5VR2BModel as R1VCCIOVCCIIPCI Clamp5.0-V DeviceMAX II MultiVolt Core FeatureMAX II MultiVolt Core FeatureRegulated devices support 3.3-V or 2.5-V VCC Normal ordering code Iccstandby (typical) = 12 ma Regulator-bypassed (mask change) devices support 1.8-V VCC Special “G” ordering code Iccstandby (typical) = 2 maMultiVolt I/O SupportMultiVolt I/O SupportSignals with VCCIO of 3.3 V exceeds vth for device with 5.0-V TTL inputs Requires external pull-up resistors & PCI diode enabled for device with 5.0-V CMOS inputs Requires external series resistors & PCI clamping diode enabled (1),(2)(3)MAX II MultiVolt End ApplicationMAX II MultiVolt End ApplicationBus bridging system Use as voltage translatorNote: External resistor (and possible diode) needed for 5.0-V translation FPGAMicro- ControllerMemoryASSPMAX II MultiVolt End ApplicationMAX II MultiVolt End ApplicationMulti-voltage system power-up management Programmable Power SuppliesPower Up Detect3.3V Flash 1.8V ASSP 2.5V µP MAX II Power GoodResetsUser Flash Memory User Flash Memory Feature Flash memory storage bank 8,192 bits per device Interface to SPI, parallel, I2C or proprietary buses Applications Store revision & serial number data Store boot-up & configuration data Industry First!More UFM Features More UFM Features Store data up to 16 bits wide Two sectors for partitioned sector erase Built-in, non-programmable oscillator Program, erase & busy signals Auto-increment addressingMAX II User Flash Memory Block MAX II User Flash Memory Block CFMQuartus generated interface logic Parallel-serial SPI-serial I2C-serial None Parallel SPI I2CUFMUFM Array DescriptionUFM Array DescriptionUFM Array Description UFM Memory OrganizationUFM Data & Address Control BlocksUFM Data & Address Control BlocksSerial address shift register Supports auto-increment addressing with ARSHIFT signal Maximum ARCLK of 10 MHz Most significant bit (MSB) indicates sector Serial data shift register MSB shifted in & out first Maximum DRCLK of 10 MHz Programming & Erasing UFMProgramming & Erasing UFMCFM & UFM block guaranteed for 100 erase/program cycles UFM erased bits are 1’s 1’s act as don’t care/mask in a write/program Each word can be programmed twice before erase requiredInternal OscillatorInternal OscillatorUsed to create internal UFM program & erase sequence Enabled by OSC_ENA input Must be asserted during program or erase Can be turned off if desired The OSC output available to logic array Internal oscillator frequency divided by four, i.e. 3.3 MHz to 5.5 MHz ALTUFM MegafunctionALTUFM MegafunctionUse MegaWizard to configure Supported auto-generated logic interfaces Serial peripheral interface (SPI) Parallel I2C None (no LE logic, just Altera proprietary interface) ALTUFM Resource UsageALTUFM Resource UsageMegafunction generates additional logic to support interfacesALTUFM Megafunction Interface LE SizesProgramming MAX IIProgramming MAX IIAll MAX 7000 JTAG methods supported Jam, JBC, POF, SVF, 1532 Program CFM & UFM only No JTAG or external access to SRAM array Quartus II programmer only Altera tool supporting MAX II programming Conventional programming support from BP Micro Sytems, System General, Data I/OProgramming Options for MAX IIProgramming Options for MAX IIProgram CFM & UFM together Program CFM only Does not interfere with user data in UFM Program UFM only Program through logic array interface or conventional programming Does not affect contents in configuration flashMAX II ISP Programming TimesMAX II ISP Programming Times* Theoretical times based on a constant TCK clocking at specified rate. ** Based on packet throughput limitations through parallel or USB port.EPM240EPM570EPM1270EPM22107512AEIEEE 1532 SupportIEEE 1532 SupportDefinition Extension of 1149.1 (JTAG-boundary scan testing) Hardware & software algorithm standard Two files needed 1532 BSDL file Contains programming algorithm & description Extension of standard BSDL files Download from http://www.altera.com/support/devices/bsdl/bsdl.Html In-system configuration (ISC) file Contains programming data Generated by Quartus IIDesign SecurityDesign SecurityEnable MAX II security bit Prevents reading of configuration flash memory No SRAM access to outside world Does not secure UFM contents Flash die cannot be “hacked” to erase security bit Similar to MAX EEPROMReal-Time ISPReal-Time ISPUpdate device’s program while in operation Reduce system downtime for ISP update Change immediately or wait until next power cycle Supported through JTAG Application examples Field upgrades of fault-tolerant systems Servers/disk storage systems Diagnostic design for manufacturing; convert to functional designCore Logic ArrayConfiguration Flash Memory Block10110001JTAG Translator BlockJTAG Translator BlockProvides ability for MAX II JTAG block to drive to/from logic array Uses USER0 & USER1 JTAG instructions Allows creation of various JTAG appliances Example: parallel flash loader (PFL) feature Use MAX II to program non-JTAG-enabled flash devices Ideal when MAX II used as FPGA configuration controller from general purpose flash devices Use MAX II to speed up manufacturing programming of non-JTAG flash devicesParallel Flash Loader MegafunctionParallel Flash Loader MegafunctionPrograms CFI flash using MAX II JTAG translator Controls FPGA configuration & in-system updates Use single page to store images for single chain of devices Store up to 8 different pages of images Configure using the MegaWizardParallel Flash LoaderParallel Flash LoaderCFI Flash ChipI/O Pins for Parallel Flash Loader MegafunctionProgrammable LogicI/O RingJTAG State MachineJTAG CommandsParallel Flash Loader*Example: Flash chipMAX & MAX II ComparisonMAX & MAX II ComparisonDesigning with Quartus II Software for CPLDsDesigning with Quartus II Software for CPLDsProgramming/ConfigurationProgramming/ConfigurationProgramming/ConfigurationSetting device options Assembler module Programmer & chain description file Programming directly with Quartus II Using Parallel Flash LoaderSetting Device OptionsSetting Device OptionsDevice options control configuration & initialization of deviceAssignments  Device  Device & Pin OptionsGeneral TabGeneral TabDevice options not dependent on programming method Enable device-wide clear Enable device-wide output enable Enable security bitProgramming Files TabProgramming Files TabOutput files always created POF (Programming Object File) Other selectable output files JAM (JEDEC STAPL) JBC (JAM Byte-Code) HEXOUT (Intel Hex Format) SVF (Serial Vector Format) ISC File Support in Future ReleaseUnused Pins TabUnused Pins TabIndicates state of all unused I/O pins after configuration is complete All unused pins must be tri-stated when using MAX II development kitQuartus II Assembler ModuleQuartus II Assembler ModuleGenerates all programming files As selected in Device & Pin Options box Ways to run assembler Full compilation Execute assembler individually Processing menu  Start  Start Assembler Generates files without full compilation Enabling/disabling configuration device feature (ex. security bit, device-wide clear, etc.) ScriptingOpen ProgrammerOpen ProgrammerEnables device programming ByteBlaster™ II or ByteBlasterMV™ cables USB-Blaster cable MasterBlaster™ cable APU (Altera Programming Unit) Opens Chain Description File (.CDF) Stores device programming chain informationCDF FileCDF FileLists devices & files for programming or configuration Programs/configures in top-to-bottom orderWhen adding files, the device for that file is automatically chosenExample CDF FilesExample CDF FilesSingle device chainMultiple device chainProgrammer ToolbarProgrammer ToolbarStart programming Auto detect devices in JTAG chain Add/remove/change devices in chain Add/remove/changes files in chain Change order of files in chain Setup programming hardwareSetting up Programming HardwareSetting up Programming HardwareClick on the Hardware Setup buttonUse drop-down to select programming hardwareChain Programming ModesChain Programming ModesJTAG JTAG chain consisting of Altera & non-Altera devices In-socket programming CPLDs & configuration devices in APUProgramming OptionsProgramming OptionsProgram/configure Applies to all devices Verify, blank-check, examine & erase Configuration devices MAX II, MAX 7000 & MAX 3000 Security bit & ISP clamp MAX II, MAX 7000 & MAX 3000To program, verify, blank-check, examine, or erase a device, check the appropriate boxesBypassing Devices in JTAG Chain (1)Bypassing Devices in JTAG Chain (1)Method 1 : Add programming file & leave program/configure box uncheckedBypassing Devices in JTAG Chain (2)Bypassing Devices in JTAG Chain (2)Method 2 : Click on add device button & select device to leave the programming file field blankAdding Non-Altera Device to ChainAdding Non-Altera Device to ChainClick New & create user-defined devices to add non-Altera devices to chainStarting the ProgrammerStarting the ProgrammerProgress field shows the percentage of completion for the programmerClick program button once CDF file & hardware setup are completeProgramming Options ReviewProgramming Options ReviewProgram CFM & UFM together Program CFM only Program UFM only Real-Time ISP Load new program into CFM New data not downloaded to logic arrayProgramming UFM/CFMProgramming UFM/CFMEnable program/configure button for deviceProgramming UFM or CFM OnlyProgramming UFM or CFM OnlyDisable program/configure button for UFM or CFMCFM OnlyUFM OnlyEnabling Real-Time ISPEnabling Real-Time ISPEnable real-time button in ProgrammerUsing Parallel Flash LoaderUsing Parallel Flash LoaderMemory space Configuring PFL Creating PFL programming files Programming flash See Application Note 386 “Using the MAX II Parallel Flash Loader with the Quartus II Software” for more detailsMemory SpaceMemory SpaceEach page configures a single FPGA configuration chain Store up to 8 pages of images User or Quartus II-controlled page boundaries supported Option bits Location specified by designer Stores Page starting addresses Page-Valid flags0x000000x200000x400000x600000xF0000Example SpaceConfiguring PFL Block Configuring PFL Block Input Clock Frequency*Flash SizeOption Bits AddressFPGA Configuration Scheme (Serial vs. Parallel)Flash Data WidthNote: This clock is used for FPGA configuration and flash programmingCreating PFL Programming FilesCreating PFL Programming FilesConvert FPGA SOF & HEX data files into MAX II POF fileFile  Convert Programming FilesFlash SizeSingle page configuration chainHighlight “SOF Data” & click “Add File” to add FPGA configuration filesClick to generate POFAdditional PagesAdditional PagesAdd