VFC32 电压—频率 频率—电压转换器

® VFC32 International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 FEATURES l OPERATION UP TO 500kHz l EXCELLENT LINEARITY – 0.01% max at 10kHz FS – 0.05% max at 100kHz FS l V/F OR F/V CONVERSION l MONOTONIC l VOLTAGE OR CURRENT INPUT APPLICATIONS l INTEGRATING A/D CONVERTER l SERIAL FREQUENCY OUTPUT l ISOLATED DATA TRANSMISSION l FM ANALOG SIGNAL MOD/DEMOD l MOTOR SPEED CONTROL l TACHOMETER DESCRIPTION The VFC32 voltage-to-frequency converter provides an output frequency accurately proportional to its input voltage. The digital open-collector frequency output is compatible with all common logic families. Its integrating input characteristics give the VFC32 excellent noise immunity and low nonlinearity. Full-scale output frequency is determined by an exter- nal capacitor and resistor and can be scaled over a wide range. The VFC32 can also be configured as a frequency-to-voltage converter. The VFC32 is available in 14-pin plastic DIP, SO-14 surface-mount, and metal TO-100 packages. Commer- cial, industrial, and military temperature range models are available. Voltage-to-Frequency and Frequency-to-Voltage CONVERTER –In One-Shot +VCC fOUT –VCC VFC32 Common +In Comparator InputVOUT One-Shot Capacitor ©1977 Burr-Brown Corporation PDS-372G Printed in U.S.A. October, 1998 2VFC32 SPECIFICATIONS At TA = +25° C and VCC = – 15V, unless otherwise noted. ] Specification the same as VFC32KP. NOTES: (1) A 25% duty cycle (0.25mA input current) is recommended for best linearity. (2) Adjustable to zero. See Offset and Gain Adjustment section. (3) Linearity error is specified at any operating frequency from the straight line intersecting 90% of full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. Above 200kHz, it is recommended all grades be operated below +85° C. (4) – 0.015% of FSR for negative inputs shown in Figure 5. Positive inputs are shown in Figure 1. (5) FSR = Full Scale Range (corresponds to full scale frequency and full scale input voltage). (6) Exclusive of external components’ drift. (7) Positive drift is defined to be increasing frequency with increasing temperature. (8) For operations above 200kHz up to 500kHz, see Discussion of Specifications and Installation and Operation sections. (9) One pulse of new frequency plus 1m s. VFC32KP, KU VFC32BM VFC32SM PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT (V/F CONVERTER) FOUT = VIN/7.5 R1 C1 Voltage Range(1) Positive Input >0 +0.25mA ] ] ] ] V x R1 Negative Input >0 –10 ] ] ] ] V Current Range(1) >0 +0.25 ] ] ] ] mA Bias Current Inverting Input 20 100 ] ] ] ] nA Noninverting Input 100 250 ] ] ] ] nA Offset Voltage(2) 1 4 ] ] ] ] mV Differential Impedance 300 || 10 650 || 10 ] ] ] ] kW || pF Common-mode Impedance 300 || 3 500 || 3 ] ] ] ] M W || pF INPUT (F/V CONVERTER) VOUT = 7.5 R1 C1 FIN Impedance 50 || 10 150 || 10 ] ] ] ] kW || pF Logic “1” +1.0 ] ] ] ] V Logic “0” –0.05 ] ] ] ] V Pulse-width Range 0.1 150k/FMAX ] ] ] ] m s ACCURACY Linearity Error(3) 0.01Hz £ Oper Freq £ 10kHz – 0.005 – 0.010(4) ] ] ] ] % of FSR(5) 0.1Hz £ Oper Freq £ 100kHz – 0.025 – 0.05 ] ] ] ] % of FSR 0.5Hz £ Oper Freq £ 500kHz – 0.05 ] ] % of FSR Offset Error Input Offset Votlage(2) 1 4 ] ] ] ] mV Offset Drift(6) – 3 ] ] ppm of FSR/° C Gain Error(2) 5 ] ] % of FSR Gain Drift(6) f = 10kHz – 75 – 50 – 100 – 70 – 150 ppm/ ° C Full Scale Drift f = 10kHz – 75 – 50 – 100 – 70 – 150 ppm of FSR/° C (offset drift and gain drift)(6, 7) Power Supply f = DC, – VCC = 12VDC Sensitivity to 18VDC – 0.015 ] ] % of FSR/% OUTPUT (V/F CONVERTER) (open collector output) Voltage, Logic “0” ISINK = 8mA 0 0.2 0.4 ] ] ] ] ] ] V Leakage Current, Logic “1” VO = 15V 0.01 1.0 ] ] ] ] m A Voltage, Logic “1” External Pull-up Resistor Required (see Figure 4) VPU ] ] V Pulse Width For Best Linearity 0.25/FMAX ] ] s Fall Time IOUT = 5mA, CLOAD = 500pF 400 ] ] ns OUTPUT (F/V CONVERTER) VOUT Voltage IO £ 7mA 0 to +10 ] ] V Current VO £ 7VDC +10 ] ] mA Impedance Closed Loop 1 ] ] W Capacitive Load Without Oscillation 100 ] ] pF DYNAMIC RESPONSE Full Scale Frequency 500(8) ] ] kHz Dynamic Range 6 ] ] decades Settling Time (V/F) to Specified Linearity for a Full Scale Input Step (9) ] ] Overload Recovery < 50% Overload (9) ] ] POWER SUPPLY Rated Voltage – 15 V Voltage Range – 11 – 20 ] V Quiescent Current – 5.5 – 6.0 ] ] ] mA TEMPERATURE RANGE Specification 0 +70 –25 +85 –55 +125 ° C Operating –25 +85 –55 +125 –55 +125 ° C Storage –25 +85 –65 +150 –65 +150 ° C 3 VFC32 Supply Voltage ................................................................................... – 22V Output Sink Current (FOUT) ................................................................ 50mA Output Current (VOUT) ...................................................................... +20mA Input Voltage, –Input ..................................................................... – Supply Input Voltage, +Input ..................................................................... – Supply Comparator Input .......................................................................... – Supply Storage Temperature Range: VFC32BM, SM ............................................................. –65 ° C to +150° C VFC32KP, KU ................................................................ –25 ° C to +85° C ABSOLUTE MAXIMUM RATINGS The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN CONFIGURATIONS Top View +VCC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Input Amp Sw itc h One- shot NC NC –VCC fOUT –In NC One-Shot Capacitor VOUT Common +In NC NC Comparator Input P Package U Package (Epoxy Dual-in-line) +VCC Switch NC –VCC (Case) fOUT +In One-Shot Capacitor Common –In Comparator Input M Package (TO-100) 1 3 4 5 6 7 8 9 10 VOUT NC = no internal connection External connection permitted. 2 One- shot Input Amp ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifi- cations.PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER(1) RANGE VFC32KP 14-Pin Plastic DIP 010 0° C to 70 ° C VFC32BM TO-100 Metal 007 –25 ° C to +85° C VFC32SM TO-100 Metal 007 –55 ° C to +125° C VFC32KU SO-14 SOIC 235 0° C to +70° C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION 4VFC32 TYPICAL PERFORMANCE CURVES At TA = +25° C and VCC = – 15V, unless otherwise noted. 1k 1M Full Scale Frequency (Hz) 0.10 0.001 Ty pi ca l L in ea rit y Er ro r ( % of FS R) 10k 100k 0.01 TA = +25°C LINEARITY ERROR vs FULL SCALE FREQUENCY Duty Cycle = 25% at Full Scale 0 10k Operating Frequency (Hz) 1 –1.0 Li ne ar ity E rro r ( Hz ) 1k 7k 0 LINEARITY ERROR vs OPERATING FREQUENCY 2k 3k 4k 5k 6k 8k 9k 0.5 –0.5 fFULL SCALE = 10kHz, 25% Duty Cycle TA = +25°C 1k 1M Full Scale Frequency (Hz) 1000 10F ul l S ca le T em p Dr ift (p pm of FS R/ °C ) 10k 100k 100 (SM, KP, KU) FULL SCALE DRIFT vs FULL SCALE FREQUENCY (BM) 5 VFC32 APPLICATION INFORMATION Figure 1 shows the basic connection diagram for frequency- to-voltage conversion. R1 sets the input voltage range. For a 10V full-scale input, a 40k W input resistor is recommended. Other input voltage ranges can be achieved by changing the value of R1. R1 should be a metal film type for good stability. Manufac- turing tolerances can produce approximately – 10% variation in output frequency. Full-scale output frequency can be trimmed by adjusting the value of R1—see Figure 3. The full-scale output frequency is determined by C1. Values shown in Figure 1 are for a full-scale output frequency of 10kHz. Values for other full-scale frequencies can be read from Figure 2. Any variation in C1—tolerance, temperature drift, aging—directly affect the output frequency. Ceramic NPO or silver-mica types are a good choice. For full-scale frequencies above 200kHz, use larger capaci- tor values as indicated in Figure 2, with R1 = 20kW . The value of the integrating capacitor, C2, does not directly influence the output frequency, but its value must be chosen within certain bounds. Values chosen from Figure 2 produce approximately 2.5Vp-p integrator voltage waveform. If C2’s value is made too low, the integrator output voltage can exceed its linear output swing, resulting in a nonlinear response. Using C2 values larger than shown in Figure 2 is acceptable. Accuracy or temperature stability of C2 is not critical be- cause its value does not directly affect the output frequency. For best linearity, however, C2 should have low leakage and low dielectric absorption. Polycarbonate and other film capacitors are generally excellent. Many ceramic types are adequate, but some low-voltage ceramic capacitor types may degrade nonlinearity. Electrolytic types are not recom- mended. FREQUENCY OUTPUT PIN The frequency output terminal is an open-collector logic output. A pull-up resistor is usually connected to a 5V logic supply to create standard logic-level pulses. It can, however, be connected to any power supply up to +VCC. Output pulses have a constant duration and positive-going during the one- shot period. Current flowing in the open-collector output transistor returns through the Common terminal. This termi- nal should be connected to logic ground. (1) FIGURE 1. Voltage-to-Frequency Converter Circuit. fO VINT VIN One-Shot +15V fOUT 0 to 10kHz VINT C2 R1 40k W 0 to 10V 10nF film 0.1µF –15V 0.1µF C1 3.3nF NPO Ceramic +5V RPU 4.7k W VFC32 Pinout shown is for DIP or SOIC packages. Pull-Up Voltage 0V £ VPU £ +VCC VPU RPU £ 8mA R1 = VFS 0.25mA 6VFC32 PRINCIPLES OF OPERATION The VFC32 operates on a principle of charge balance. The signal input current is equal to VIN/R1. This current is integrated by input op amp and C2, producing a downward ramping integrator output voltage. When the integrator out- put ramps to the threshold of the comparator, the one-shot is triggered. The 1mA reference current is switched to the integrator input during the one-shot period, causing the integrator output ramp upward. After the one-shot period, the integrator again ramps downward. The oscillation process forces a long-term balance of charge (or average current) between the input signal current and the reference current. The equation for charge balance is: Where: fO is the output frequency tOS is the one-shot period, equal to tOS = 7500 C1 (Farads) (4) The values suggested for R1 and C1 are chosen to produce a 25% duty cycle at full-scale frequency output. For full-scale frequencies above 200kHz, the recommended values pro- duce a 50% duty cycle. FREQUENCY-TO-VOLTAGE CONVERSION Figure 4 shows the VFC32 connected as a frequency-to- voltage converter. The capacitive-coupled input network C3, R6 and R7 allow standard 5V logic levels to trigger the comparator input. The comparator triggers the one-shot on the falling edge of the frequency input pulses. Threshold voltage of the comparator is approximately –0.7V. For frequency input waveforms less than 5V logic levels, the R6/R7 voltage divider can be adjusted to a lower voltage to assure that the comparator is triggered. The value of C1 is chosen from Figure 2 according to the full-scale input frequency. C2 smooths the output voltage waveform. Larger values of C2 reduce the ripple in the output voltage. Smaller values of C2 allow the output voltage to settle faster in response to a change in input frequency. Resistor R1 can be trimmed to achieve the desired output voltage at the full-scale input frequency. IIN = IR(AVERAGE) (2) VIN R1 = f OtOS(1mA) (3) 1k 1M Full Scale Frequency (Hz) 0.1µF 10nF 1nF 100pF 10pF Ca pa cit or V al ue 10k 100k C2 R1 = 20kW 66,000pF fFS (kHz) Above 200kHz Full-Scale C1 = – 30pF R1 = 40kW 33,000pF fFS (kHz) C1 = – 30pF FIGURE 2. Capacitor Value Selection. FIGURE 3. Gain and Offset Voltage Trim Circuit. Pinout shown is for DIP and SOIC packages. VIN One-Shot 13 10 12 +15V 7 11 fO VINTC2 0.1µF 1 14 35kW Gain Trim 4 –15V 5 C1 33nF +5V 4.7kW VFC32 +15V 100kW –15V 10MW Offset Trim 10kW 1mA 7 VFC32 FIGURE 4. Frequency-to-Voltage Converter Circuit. FIGURE 5. V/F Converter—Negative Input Voltage. One-Shot 13 10 7 11 C2 2nF 1 14 5 C1 650pF VFC32 +5V 12 +15V fOUT 0 to 50kHz 0.1µF 4 –15V 0.1µF VIN R1 40kW Pinout shown is for DIP or SOIC package. Nonlinearity may be higher than specified due to common-mode voltage on op amp input. 0V to –10V fIN One-Shot 13 10 12 +15V 7 11 NC C2 0.1µF 1 14 4 –15V 5 C1 3.3nF VFC32 +15V –15V VO 0 to 10V +15V 12k W 2.2kW 500pF0 to 10kHz 5V Logic Input 100k W 10M W R1 40k W 2.5V 0V –2.5V 0V 电子爱好者 网站是一个面向广大电子爱好者 大专院校学生 中小型企业工程 技术人员的电子技术应用 推广专业网站 主要有 电子技术应用交流 器件资料 电子设计软件下载 电子技术支持服务 电子产品发布 转让和引进等信息 本资料或软件由"电子爱好者"网站收集整理 版权属原作者 在使用本资料或软件时 有什么问题 欢迎到 电子爱好者 网站内的 BBS技术 论坛 中发 我站的热心网友会帮助你的 技术论坛 http://www.etuni.com/bbs/index.asp 需要更多的电子技术相关资料或软件 欢迎到 电子爱好者 网站下载 电子爱好者 网站 http://www.etuni.com