IS61LV5128AL-12K

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. C 04/15/05 IS61LV5128AL ISSI® Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES • High-speed access times: 10, 12 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply • Packages available: – 36-pin 400-mil SOJ – 36-pin miniBGA – 44-pin TSOP (Type II) • Lead-free available DESCRIPTION The ISSI IS61LV5128AL is a very high-speed, low power, 524,288-word by 8-bit CMOS static RAM. The IS61LV5128AL is fabricated using ISSI's high-perform- ance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. The IS61LV5128AL operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV5128AL is available in 36-pin 400-mil SOJ, 36- pin mini BGA, and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A18 CE OE WE 512K X 8 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05 IS61LV5128AL ISSI ® PIN CONFIGURATION 36 mini BGA PIN DESCRIPTIONS A0-A18 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports VDD Power GND Ground NC No Connection TRUTH TABLE Mode WEWEWEWEWE CECECECECE OEOEOEOEOE I/O Operation VDD Current Not Selected X H X High-Z ISB1, ISB2 (Power-down) Output Disabled H L H High-Z ICC Read H L L DOUT ICC Write L L X DIN ICC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VDD I/O5 I/O4 A14 A13 A12 A11 A10 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND VDD I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC 44 43 42 41 44-Pin TSOP (Type II) 1 2 3 4 5 6 A B C D E F G H A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9 A1 A2 OE A10 NC WE NC A18 CE A11 A3 A4 A5 A17 A16 A12 A6 A7 A15 A13 A8 I/O0 I/O1 VDD GND I/O2 I/O3 A14 36-Pin SOJ Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. C 04/15/05 IS61LV5128AL ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to VDD + 0.5 V TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE VDD Range Ambient Temperature 10ns 12ns Commercial 0°C to +70°C 3.3V +10%, -5% 3.3V +10% Industrial -40°C to +85°C 3.3V +10%, -5% 3.3V +10% CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input/Output Capacitance VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05 IS61LV5128AL ISSI ® DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. –2 2 µA Ind. –5 5 ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –2 2 µA Ind. –5 5 Note: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 -12 Symbol Parameter Test Conditions Min. Max. Min. Max. Unit ICC VDD Dynamic Operating VDD = Max., Com. — 90 — 85 mA Supply Current IOUT = 0 mA, f = fMAX Ind. — 95 — 90 ISB TTL Standby Current VDD = Max., Com. — 40 — 35 mA (TTL Inputs) VIN = VIH or VIL Ind. — 45 — 40 CE ≥ VIH, f = fMAX. ISB1 TTL Standby Current VDD = Max., Com. — 20 — 20 mA (TTL Inputs) VIN = VIH or VIL Ind. — 25 — 25 CE ≥ VIH, f = 0 ISB2 CMOS Standby VDD = Max., Com. — 15 — 15 mA Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 20 — 20 VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. C 04/15/05 IS61LV5128AL ISSI ® AC TEST LOADS AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1 and 2 Figure 1 Figure 2 319 Ω 30 pF Including jig and scope 353 Ω OUTPUT 3.3V 319 Ω 5 pF Including jig and scope 353 Ω OUTPUT 3.3V READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -10 -12 Symbol Parameter Min. Max. Min. Max. Unit tRC Read Cycle Time 10 — 12 — ns tAA Address Access Time — 10 — 12 ns tOHA Output Hold Time 2 — 2 — ns tACE CE Access Time — 10 — 12 ns tDOE OE Access Time — 4 — 5 ns tHZOE(2) OE to High-Z Output — 4 — 5 ns tLZOE(2) OE to Low-Z Output 0 — 0 — ns tHZCE(2 CE to High-Z Output 0 4 0 6 ns tLZCE(2) CE to Low-Z Output 3 — 3 — ns tPU Power Up Time 0 — 0 — ns tPD Power Down Time — 10 — 12 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05 IS61LV5128AL ISSI ® t RC t OHAt AA t DOE t LZOE t ACE t LZCE t HZOE HIGH-Z DATA VALID CE_RD2.eps ADDRESS OE CE DOUT t HZCE READ CYCLE NO. 2(1,3) (CE and OE Controlled) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) DATA VALID READ1.eps PREVIOUS DATA VALID t AA t OHA t OHA t RC DOUT ADDRESS Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. C 04/15/05 IS61LV5128AL ISSI ® AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) DATA UNDEFINED t WC VALID ADDRESS t SCE t PWE1 t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CE WE DOUT DIN DATAIN VALID t LZWE t SD CE_WR1.eps WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -10 -12 Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 10 — 12 — ns tSCE CE to Write End 8 — 8 — ns tAW Address Setup Time 8 — 8 — ns to Write End tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1 WE Pulse Width 8 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 10 — 12 — ns tSD Data Setup to Write End 6 — 6 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 5 — 6 ns tLZWE(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05 IS61LV5128AL ISSI ® Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. DATA UNDEFINED LOW t WC VALID ADDRESS t PWE1 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CE WE DOUT DIN OE DATAIN VALID t LZWE t SD CE_WR2.eps WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) DATA UNDEFINED t WC VALID ADDRESS LOW LOW t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CE WE DOUT DIN OE DATAIN VALID t LZWE t SD CE_WR3.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. C 04/15/05 IS61LV5128AL ISSI ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 IS61LV5128AL-10K 400-mil Plastic SOJ 10 IS61LV5128AL-10T TSOP (Type II) 12 IS61LV5128AL-12K 400-mil Plastic SOJ 12 IS61LV5128AL-12T TSOP (Type II) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 10 IS61LV5128AL-10KI 400-mil Plastic SOJ 10 IS61LV5128AL-10KLI 400-mil Plastic SOJ, Lead-free 10 IS61LV5128AL-10TI TSOP (Type II) 10 IS61LV5128AL-10TLI TSOP (Type II), Lead-free 10 IS61LV5128AL-10BI mini BGA (8mmx10mm) 10 IS61LV5128AL-10BLI mini BGA (8mmx10mm), Lead-free 12 IS61LV5128AL-12TI TSOP (Type II) PACKAGING INFORMATION ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 01/15/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Mini Ball Grid Array Package Code: B (36-pin) Notes: 1. Controlling dimensions are in millimeters. mBGA - 6mm x 8mm MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 36 36 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — D 7.90 8.00 8.10 0.311 0.315 0.319 D1 5.25BSC 0.207BSC E 5.90 6.00 6.10 0.232 0.236 0.240 E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC b 0.30 0.35 0.40 0.012 0.014 0.016 mBGA - 8mm x 10mm MILLIMETER INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 36 36 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — D 9.90 10.00 10.10 0.390 0.394 0.398 D1 5.25BSC .207BSC E 7.90 8.00 8.10 0.311 0.315 0.319 E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC b 0.30 0.35 0.40 0.012 0.014 0.016 SEATING PLANE A A1 A2 A B C D E F G H e e D1 E1E D φ b (36x) Top View Bottom View 6 5 4 3 2 11 2 3 4 5 6 A B C D E F G H PACKAGING INFORMATION ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 400-mil Plastic SOJ Package Code: K Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. SEATING PLANE 1 N E1 D E2 E Be A1 A C A2 b N/2+1 N/2 Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) 28 32 36 A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC PACKAGING INFORMATION ISSI ® Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03 Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) 40 42 44 A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC PACKAGING INFORMATION ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Plastic TSOP Package Code: T (Type II) D SEATING PLANE be C 1 N/2 N/2+1N E1 A1 A E L α ZD . Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Plastic TSOP (T - Type II) Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max Ref. Std. No. Leads (N) 32 44 50 A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF α 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°