同步复位与异步复位

Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? Clifford E. Cummings Don Mills Sunburst Design, Inc. LCDM Engineering ABSTRACT This paper will investigate the pros and cons of synchronous and asynchronous resets. It will then look at usage of each type of reset followed by recommendations for proper usage of each type. This paper will also detail an interesting synchronization technique using digital calibration to synchronize reset removal on a multi-ASIC design. SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 2 1.0 resets, Resets, RESETS, and then there’s RESETS One cannot begin to consider a discussion of reset usage and styles without first saluting the most common reset usage of all. This undesired reset occurs almost daily in systems that have been tested, verified, manufactured, and integrated into the consumer, education, government, and military environments. This reset follows what is often called “The Blue Screen of Death” resulting from software incompatibilities between the OS from a certain software company, the software programs the OS is servicing, and the hardware on which the OS software is executing. Why be concerned with these annoying little resets anyway? Why devote a whole paper to such a trivial subject? Anyone who has used a PC with a certain OS loaded knows that the hardware reset comes in quite handy. It will put the computer back to a known working state (at least temporarily) by applying a system reset to each of the chips in the system that have or require a reset. For individual ASICs, the primary purpose of a reset is to force the ASIC design (either behavioral, RTL, or structural) into a known state for simulation. Once the ASIC is built, the need for the ASIC to have reset applied is determined by the system, the application of the ASIC, and the design of the ASIC. For instance, many data path communication ASICs are designed to synchronize to an input data stream, process the data, and then output it. If sync is ever lost, the ASIC goes through a routine to re-acquire sync. If this type of ASIC is designed correctly, such that all unused states point to the “start acquiring sync” state, it can function properly in a system without ever being reset. A system reset would be required on power up for such an ASIC if the state machines in the ASIC took advantage of “don’t care” logic reduction during the synthesis phase. It is the opinion of the authors that in general, every flip-flop in an ASIC should be resetable whether or not it is required by the system. Further more, the authors prefer to use asynchronous resets following the guidelines detailed in this paper. There are exceptions to these guidelines. In some cases, when follower flip-flops (shift register flip- flops) are used in high speed applications, reset might be eliminated from some flip-flops to achieve higher performance designs. This type of environment requires a number of clocks during the reset active period to put the ASIC into a known state. Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flip-flop receive a reset, how will the reset tree be laid out and buffered, how to verify timing of the reset tree, how to functionally test the reset with test scan vectors, and how to apply the reset among multiple clock zones. In addition, when applying resets between multiple ASICs that require a specific reset release sequence, special techniques must be employed to adjust to variances of chip and board manufacturing. The final sections of this paper will address this latter issue. 2.0 General flip-flop coding style notes 2.1 Synchronous reset flip-flops with non reset follower flip-flops Each Verilog procedural block or VHDL process should model only one type of flip-flop. In other words, a designer should not mix resetable flip-flops with follower flip-flops (flops with no resets)[12]. Follower flip-flops are flip- flops that are simple data shift registers. In the Verilog code of Example 1a and the VHDL code of Example 1b, a flip-flop is used to capture data and then its output is passed through a follower flip-flop. The first stage of this design is reset with a synchronous reset. The second stage is a follower flip-flop and is not reset, but because the two flip-flops were inferred in the same procedural block/process, the reset signal rst_n will be used as a data enable for the second flop. This coding style will generate extraneous logic as shown in Figure 1. SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 3 module badFFstyle (q2, d, clk, rst_n); output q2; input d, clk, rst_n; reg q2, q1; always @(posedge clk) if (!rst_n) q1 <= 1'b0; else begin q1 <= d; q2 <= q1; end endmodule Example 1a - Bad Verilog coding style to model dissimilar flip-flops library ieee; use ieee.std_logic_1164.all; entity badFFstyle is port ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; q2 : out std_logic); end badFFstyle; architecture rtl of badFFstyle is signal q1 : std_logic; begin process (clk) begin if (clk'event and clk = '1') then if (rst_n = '0') then q1 <= '0'; else q1 <= d; q2 <= q1; end if; end if; end process; end rtl; Example 1b - Bad VHDL coding style to model dissimilar flip-flops Figure 1 - Bad coding style yields a design with an unnecessary loadable flip-flop SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 4 The correct way to model a follower flip-flop is with two Verilog procedural blocks as shown in Example 2a or two VHDL processes as shown in Example 2b. These coding styles will generate the logic shown in Figure 2. module goodFFstyle (q2, d, clk, rst_n); output q2; input d, clk, rst_n; reg q2, q1; always @(posedge clk) if (!rst_n) q1 <= 1'b0; else q1 <= d; always @(posedge clk) q2 <= q1; endmodule Example 2a - Good Verilog coding style to model dissimilar flip-flops library ieee; use ieee.std_logic_1164.all; entity goodFFstyle is port ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; q2 : out std_logic); end goodFFstyle; architecture rtl of goodFFstyle is signal q1 : std_logic; begin process (clk) begin if (clk'event and clk = '1') then if (rst_n = '0') then q1 <= '0'; else q1 <= d; end if; end if; end process; process (clk) begin if (clk'event and clk = '1') then q2 <= q1; end if; end process; end rtl; Example 2b - Good VHDL coding style to model dissimilar flip-flops SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 5 Figure 2 - Two different types of flip-flops, one with synchronous reset and one without It should be noted that the extraneous logic generated by the code in Example 1a and Example 1b is only a result of using a synchronous reset. If an asynchronous reset approach had be used, then both coding styles would synthesize to the same design without any extra combinational logic. The generation of different flip-flop styles is largely a function of the sensitivity lists and if-else statements that are used in the HDL code. More details about the sensitivity list and if-else coding styles are detailed in section 3.1. 2.2 Flip-flop inference style Each inferred flip-flop should not be independently modeled in its own procedural block/process. As a matter of style, all inferred flip-flops of a given function or even groups of functions should be described using a single procedural block/process. Multiple procedural blocks/processes should be used to model macro level functional divisions within a given module/architecture. The exception to this guideline is that of follower flip-flops as discussed in the previous section (section 2.1) where multiple procedural blocks/processes are required to efficiently model the function itself. 2.3 Assignment operator guideline In Verilog, all assignments made inside the always block modeling an inferred flip-flop (sequential logic) should be made with nonblocking assignment operators[3]. Likewise, for VHDL, inferred flip-flops should be made using signal assignments. 3.0 Synchronous resets As research was conducted for this paper, a collection of ESNUG and SOLV-IT articles was gathered and reviewed. Around 80+% of the gathered articles focused on synchronous reset issues. Many SNUG papers have been presented in which the presenter would claim something like, “we all know that the best way to do resets in an ASIC is to strictly use synchronous resets”, or maybe, “asynchronous resets are bad and should be avoided.” Yet, little evidence was offered to justify these statements. There are some advantages to using synchronous resets, but there are also disadvantages. The same is true for asynchronous resets. The designer must use the approach that is appropriate for the design. Synchronous resets are based on the premise that the reset signal will only affect or reset the state of the flip-flop on the active edge of a clock. The reset can be applied to the flip-flop as part of the combinational logic generating the d-input to the flip-flop. If this is the case, the coding style to model the reset should be an if/else priority style with the reset in the if condition and all other combinational logic in the else section. If this style is not strictly observed, two possible problems can occur. First, in some simulators, based on the logic equations, the logic can block the reset from reaching the flip-flop. This is only a simulation issue, not a hardware issue, but remember, one of the prime objectives of a reset is to put the ASIC into a known state for simulation. Second, the reset could be a “late arriving signal” relative to the clock period, due to the high fanout of the reset tree. Even though the reset will be buffered from a reset buffer tree, it is wise to limit the amount of logic the reset must traverse once it reaches the local logic. This style of synchronous reset can be used with any logic or library. Example 3 shows an implementation of this style of synchronous reset as part of a loadable counter with carry out. SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 6 module ctr8sr ( q, co, d, ld, rst_n, clk); output [7:0] q; output co; input [7:0] d; input ld, rst_n, clk; reg [7:0] q; reg co; always @(posedge clk) if (!rst_n) {co,q} <= 9'b0; // sync reset else if (ld) {co,q} <= d; // sync load else {co,q} <= q + 1'b1; // sync increment endmodule Example 3a - Verilog code for a loadable counter with synchronous reset library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ctr8sr is port ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; ld : in std_logic; q : out std_logic_vector(7 downto 0); co : out std_logic); end ctr8sr; architecture rtl of ctr8sr is signal count : std_logic_vector(8 downto 0); begin co <= count(8); q <= count(7 downto 0); process (clk) begin if (clk'event and clk = '1') then if (rst_n = '0') then count <= (others => '0'); -- sync reset elsif (ld = '1') then count <= '0' & d; -- sync load else count <= count + 1; -- sync increment end if; end if; end process; end rtl; Example 3b - VHDL code for a loadable counter with synchronous reset SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 7 Figure 3 - Loadable counter with synchronous reset A second style of synchronous resets is based on the availability of flip-flops with synchronous reset pins and the ability of the designer and synthesis tool to make use of those pins. This is sometimes the case, but more often the first style discussed above is the implementation used[22][26]. 3.1 Coding style and example circuit The Verilog code of Example 4a and the VHDL code of 4b show the correct way to model synchronous reset flip- flops. Note that the reset is not part of the sensitivity list. For Verilog omitting the reset from the sensitivity list is what makes the reset synchronous. For VHDL omitting the reset from the sensitivity list and checking for the reset after the “if clk’event and clk = 1” statement makes the reset synchronous. Also note that the reset is given priority over any other assignment by using the if-else coding style. module sync_resetFFstyle (q, d, clk, rst_n); output q; input d, clk, rst_n; reg q; always @(posedge clk) if (!rst_n) q <= 1'b0; else q <= d; endmodule Example 4a - Correct way to model a flip-flop with synchronous reset using Verilog library ieee; use ieee.std_logic_1164.all; entity syncresetFFstyle is port ( clk : in std_logic; rst_n : in std_logic; d : in std_logic; q : out std_logic); end syncresetFFstyle; architecture rtl of syncresetFFstyle is begin process (clk) begin SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 8 if (clk'event and clk = '1') then if (rst_n = '0') then q <= '0'; else q <= d; end if; end if; end process; end rtl; Example 4b - Correct way to model a flip-flop with synchronous reset using VHDL For flip-flops designed with synchronous reset style #1 (reset is gated with data to the d-input), Synopsys has a switch that the designer can use to help infer flip-flops with synchronous resets. Compiler directive: sync_set_reset In general, the authors recommend only using Synopsys switches when they are required and make a difference; however, our colleague Steve Golson pointed out that the sync_set_reset directive does not affect the functionality of a design, so its omission would not be recognized until gate-level simulation, when discovery of a failure would require re-synthesizing the design late in the project schedule. Since this directive is only required once per module, adding it to each module with synchronous resets is recommended[19]. A few years back, another ESNUG contributor recommended adding the compile_preserve_sync_resets = "true" compiler directive[13]. Although this directive might have been useful a few years ago, it was discontinued starting with Synopsys version 3.4b[22]. 3.2 Advantages of synchronous resets Synchronous reset will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. If a design is tight, the area savings of one or two gates per flip-flop may ensure the ASIC fits into the die. However, in today’s technology of huge die sizes, the savings of a gate or two per flip-flop is generally irrelevant and will not be a significant factor of whether a design fits into a die. Synchronous reset can be much easier to work with when using cycle based simulators. For this very reason, synchronous resets are recommend in section 3.2.4(2nd edition, section 3.2.3 in the 1st edition) of the Reuse Methodology Manual (RMM)[18]. Synchronous resets generally insure that the circuit is 100% synchronous. Synchronous resets insure that reset can only occur at an active clock edge. The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the flip-flop could go metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clocks. By using synchronous resets and a number of clocks as part of the reset process, flip-flops can be used within the reset buffer tree to help the timing of the buffer tree keep within a clock period. 3.3 Disadvantages of synchronous resets Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock[14]. A designer must work with pessimistic vs. optimistic simulators. This can be an issue if the reset is generated by combinational logic in the ASIC or if the reset must traverse many levels of local combinational logic. During simulation, based on how the reset is generated or how the reset is applied to a functional block, the reset can be masked by X’s. A large number of the ESNUG articles addressed this issue. Most simulators will not resolve some X-logic conditions and therefore block out the synchronous reset[5][6][7][8][9][10][11][12][13][20]. SNUG San Jose 2002 Synchronous Resets? Asynchronous Resets? Rev 1.1 I am so confused! How will I ever know which to use? 9 By it’s very nature, a synchronous reset will require a clock in order to reset the circuit. This may not be a disadvantage to some design styles but to others, it may be an annoyance. The requirement of a clock to cause the reset condition is significant if the ASIC/FPGA has an internal tristate bus. In order to prevent bus contention on an internal tristate a tristate bus when a chip is powered up, the chip must have a power on asynchronous reset[17]. 4.0 Asynchronous resets Asynchronous resets are the authors preferred reset approach. However, asynchronous resets alone can be very dangerous. Many engineers like the idea of being able to apply the reset to their circuit and have the logic go to a known state. The biggest problem with asynchronous resets is the reset release, also called reset removal. The subject will be elaborated in detail in section 5.0. Asynchronous reset flip-flops incorporate a reset pin into the flip-flop design. The reset pin is typically active low (the flip-flop goes into the reset state when the signal attached to the flip-flop reset pin goes to a logic low level.) 4.1 Coding style and example circuit The Verilog code of Example 5a and the VHDL code of Example 5b show the correct way to model asynchronous reset flip-flops. Note that the reset is part of the sensitivity list. For Verilog, adding the reset to the sensitivity list is what makes the reset asynchronous. In order for the Verilog simulation model of an asynchronous flip-flop to simulate correctly, the sensitivity list should only be active on the leading edge of the asynchronous reset signal. Hence, in Example 5a, the always procedure block will be entered on the leading edge of the reset, then the if condition will check for the correct reset level. Synopsys requires that if any signal in the sensitivity list is edge-sensitive, then all signals in the sensitivity list must be edge-sensitive. In other words, Synopsys forces the correct coding style. Verilog simulation does not have this requirement, but if the sensitivity list were sensitive to more than just the active clock edge and the reset leading edge, the simulation model would be incorrect[4]. Additionally, only the clock and reset signals can be in the sensitivity list. If other signals are included (legal Verilog, illegal Verilog RTL synthesis coding style) the simulation model would not be correct for a flip-flop and Synopsys would report an error w