8位16进制频率计

8位16进制频率计 八位十六进制频率计 摘要 频率计又称为频率计数器，是一种专门对被测信号频率进行测量 的电子测量仪器。可用来测量频率、时间、周期、计数。该设计是利用 VHDL语言实现频率计的功能，频率计主要由四个模块构成: 计数模 块、锁存模块 显示模块以及控制模块。对各个部分的设计思路、对各 部分电路设计的选择、元器件的筛选、以及对它们的调试、对调试 结果的，最后得到实验结果的方方面面。 关键字:频率计、VHDL、元件例化。 Abstract Frequency meter is called for frequency counter ,which is a specialized measuring device to be used for measuring measured signal frequency . It can be used to measure frequency,time,period,counting.The layout make use of VHDL language to come true the function of frequency meter,it is made up of four blocks which are counting block,registering block,showing block and curbing block.Thinking ,electric circuit project design ,component screen , shakedown test and analysing result of every part,finally getting all aspects of experimenting result. Key : frequency meter, VHDL,component. 一(原理 八位十六进制频率计是由TFCTRL的计数使能信号CNT_EN能产生一个1秒脉宽的周期信号，并对频率计中的32位二进制计数器COUNTER32B的ENABL使能进行同步控制。当CNT_EN高电平时允许计数;低电平时停止计数，并保持其所计的脉冲数。在停止计数期间，首先需要一个锁存信号LOAD的上跳沿将计数器在前一秒钟的计数值锁存进各锁存器REG32B中，并由八位十六进制7段译码器译出，显示计数值。设置锁存器的好处是数据显示稳定，不会由于周期性的清零信号而不断闪烁。锁存信号后，必须有清零信号RST_CNT对计数器进行清零，为下一秒的计数操作作准备。 二(方案论证 用VHDL设计电路系统，可以把任何复杂的电路系统视为一个模块，对应一个设计实体。在VHDL层次化设计中，它所设计的模块既可以是顶层实体，又可以是较低层实体，但对不同层次模块应选择不同的描述方法。在系统的底层设计中，采用VHDL进行描述，由于其对系统很强的行为描述能力，可以不必使系统层层细化，从而避开具体的器件结构，从逻辑行为上直接对模块进行描述和设计，之后，EDA软件中的VHDL综合器将自动将程序综合成为具体FPGA,CPLD等目标芯片的网文件，无疑可使设计大为简化。 VHDL特点: 1.能形式化地抽象表示电路的行为和结构; 2. 支持逻辑设计中层次与范围地描述; 1 3. 可借用高级语言地精巧结构来简化电路行为和结构;具有电路仿 真与验证机制以保证设计的正确性; out 4. 支持电路描述由高层到低层的综合转换; 5. 硬件描述和实现工艺无关; 显示模块 6. 便于文档管理 7. 易于理解和设计重用 锁存模块 CLK 计数模块 控制模块 fin 总体框图 三(各模块的实现和功能仿真 1、测频控制模块 设计频率计的关键是设计一个测频率控制信号发生器，产生测量频率的控制时序。控制时钟信号clk1取为1Hz，2分频后即可查声一个脉宽为1秒的时钟cnt-en，一此作为计数闸门信号。当cnt-en为高电平时，允许计数;当cnt-en由高电平变为低电平(下降沿到来)时，应 2 产生一个锁存信号，将计数值保存起来;锁存数据后，还要在下次cnt-en上升沿到来之前产生零信号rst_en，将计数器清零，为下次计数 作准备。 程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FIC1 IS PORT (CLK1:IN STD_LOGIC; CNT: OUT STD_LOGIC; RST:OUT STD_LOGIC; LOAD:OUT STD_LOGIC); END FIC1; ARCHITECTURE one OF FIC1 IS SIGNAL M: STD_LOGIC; BEGIN PROCESS (CLK1) BEGIN IF CLK1 'EVENT AND CLK1='1' THEN M<= NOT M; END IF; END PROCESS; PROCESS (CLK1,M) BEGIN IF CLK1='0' AND M='0' THEN RST<='1'; ELSE RST <='0'; END IF; 3 END PROCESS; LOAD <= NOT M; CNT <=M; END one; 仿真结果: 2.计数模块 计数器以待测信号作为时钟,清零信号rst到来时,异步清零;cnt-en为 高电平时开始计数。计数是以十进制数 显示,本文设计了一个简单的10kHz以 内信号的频率机计，如果需要测试较高 的频率信号，则将cout的输出位数增 加，当然锁存器的位数也要增加 。 程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT32 IS PORT (CLR:IN STD_LOGIC; EN:IN STD_LOGIC; FIN:IN STD_LOGIC; 4 COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END CNT32; ARCHITECTURE two OF CNT32 IS SIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN PROCESS (CLR,EN,FIN) BEGIN IF CLR='1' THEN CQI <= (OTHERS=>'0'); ELSIF FIN 'EVENT AND FIN='1' THEN IF EN='1' THEN CQI <= CQI+1; END IF; END IF; END PROCESS; COUT <=CQI; END two; 仿真结果: 3、锁存模块 当cnt-en下降沿到来时，将计数器 的计数值锁存，这样可由外部的七段译码器 译码并在数码管显示。设置锁存器的好处是显示的数据稳定，不会由于周期性的清零信号而不断闪烁。锁存器的位数应跟计数器完全一样。 程序: LIBRARY IE EE; 5 USEIEEE.STD_LOGIC_1164.ALL; ENTITY REG32A IS PORT( LK :IN STD_LOGIC; DIN:INSTD_LOGIC_VECTOR (31 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); END REG32A; ARCHITECTURE three OF REG32A IS BEGIN PROCESS (LK,DIN) BEGIN IF LK 'EVENT AND LK='1' THEN DOUT <=DIN; END IF; END PROCESS; END three; 仿真结果: 4.显示模块 在停止计数期间，首先需要一个锁存信号 LOAD的上跳沿将计数器在前一秒钟的计数值 锁存进各锁存器REG32B中，并由八位十六进 制7段译码器译出，显示计数值。 程序: LIBRARY IEEE; 6 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DECL7S IS PORT (Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0); LED7S1,LED7S2,LED7S3,LED7S4,LED7S5,LED7S6, LED7S7,LED7S8:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END ENTITY DECL7S; ARCHITECTURE four OF DECL7S IS BEGIN PROCESS(Q) VARIABLE Q1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q1:=Q(0) & Q(1) &Q(2) & Q(3); CASE Q1 IS WHEN "0000"=>LED7S1<="0111111"; WHEN "0001"=>LED7S1<="0000110"; WHEN "0010"=>LED7S1<="1011011"; WHEN "0011"=>LED7S1<="1001111"; WHEN "0100"=>LED7S1<="1100110"; WHEN "0101"=>LED7S1<="1101101"; WHEN "0110"=>LED7S1<="1111101"; WHEN "0111"=>LED7S1<="0000111"; WHEN "1000"=>LED7S1<="1111111"; WHEN "1001"=>LED7S1<="1101111"; WHEN "1010"=>LED7S1<="1110111"; WHEN "1011"=>LED7S1<="1111100"; WHEN "1100"=>LED7S1<="0111001"; WHEN "1101"=>LED7S1<="1011110"; WHEN "1110"=>LED7S1<="1111011"; 7 WHEN "1111"=>LED7S1<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q2:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q2:=Q(4)&Q(5)&Q(6)&Q(7); CASE Q2 IS WHEN "0000"=>LED7S2<="0111111"; WHEN "0001"=>LED7S2<="0000110"; WHEN "0010"=>LED7S2<="1011011"; WHEN "0011"=>LED7S2<="1001111"; WHEN "0100"=>LED7S2<="1100110"; WHEN "0101"=>LED7S2<="1101101"; WHEN "0110"=>LED7S2<="1111101"; WHEN "0111"=>LED7S2<="0000111"; WHEN "1000"=>LED7S2<="1111111"; WHEN "1001"=>LED7S2<="1101111"; WHEN "1010"=>LED7S2<="1110111"; WHEN "1011"=>LED7S2<="1111100"; WHEN "1100"=>LED7S2<="0111001"; WHEN "1101"=>LED7S2<="1011110"; WHEN "1110"=>LED7S2<="1111011"; WHEN "1111"=>LED7S2<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q3:STD_LOGIC_VECTOR(3 DOWNTO 0); 8 BEGIN Q3:=Q(8)&Q(9)&Q(10)&Q(11); CASE Q3 IS WHEN "0000"=>LED7S3<="0111111"; WHEN "0001"=>LED7S3<="0000110"; WHEN "0010"=>LED7S3<="1011011"; WHEN "0011"=>LED7S3<="1001111"; WHEN "0100"=>LED7S3<="1100110"; WHEN "0101"=>LED7S3<="1101101"; WHEN "0110"=>LED7S3<="1111101"; WHEN "0111"=>LED7S3<="0000111"; WHEN "1000"=>LED7S3<="1111111"; WHEN "1001"=>LED7S3<="1101111"; WHEN "1010"=>LED7S3<="1110111"; WHEN "1011"=>LED7S3<="1111100"; WHEN "1100"=>LED7S3<="0111001"; WHEN "1101"=>LED7S3<="1011110"; WHEN "1110"=>LED7S3<="1111011"; WHEN "1111"=>LED7S3<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q4:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q4:=Q(12)&Q(13)&Q(14)&Q(15); CASE Q4 IS WHEN "0000"=>LED7S4<="0111111"; WHEN "0001"=>LED7S4<="0000110"; WHEN "0010"=>LED7S4<="1011011"; 9 WHEN "0011"=>LED7S4<="1001111"; WHEN "0100"=>LED7S4<="1100110"; WHEN "0101"=>LED7S4<="1101101"; WHEN "0110"=>LED7S4<="1111101"; WHEN "0111"=>LED7S4<="0000111"; WHEN "1000"=>LED7S4<="1111111"; WHEN "1001"=>LED7S4<="1101111"; WHEN "1010"=>LED7S4<="1110111"; WHEN "1011"=>LED7S4<="1111100"; WHEN "1100"=>LED7S4<="0111001"; WHEN "1101"=>LED7S4<="1011110"; WHEN "1110"=>LED7S4<="1111011"; WHEN "1111"=>LED7S4<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q5:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q5:=Q(16)&Q(17)&Q(18)&Q(19); CASE Q5 IS WHEN "0000"=>LED7S5<="0111111"; WHEN "0001"=>LED7S5<="0000110"; WHEN "0010"=>LED7S5<="1011011"; WHEN "0011"=>LED7S5<="1001111"; WHEN "0100"=>LED7S5<="1100110"; WHEN "0101"=>LED7S5<="1101101"; WHEN "0110"=>LED7S5<="1111101"; WHEN "0111"=>LED7S5<="0000111"; WHEN "1000"=>LED7S5<="1111111"; 10 WHEN "1001"=>LED7S5<="1101111"; WHEN "1010"=>LED7S5<="1110111"; WHEN "1011"=>LED7S5<="1111100"; WHEN "1100"=>LED7S5<="0111001"; WHEN "1101"=>LED7S5<="1011110"; WHEN "1110"=>LED7S5<="1111011"; WHEN "1111"=>LED7S5<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q6:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q6:=Q(20)&Q(21)&Q(22)&Q(23); CASE Q6 IS WHEN "0000"=>LED7S6<="0111111"; WHEN "0001"=>LED7S6<="0000110"; WHEN "0010"=>LED7S6<="1011011"; WHEN "0011"=>LED7S6<="1001111"; WHEN "0100"=>LED7S6<="1100110"; WHEN "0101"=>LED7S6<="1101101"; WHEN "0110"=>LED7S6<="1111101"; WHEN "0111"=>LED7S6<="0000111"; WHEN "1000"=>LED7S6<="1111111"; WHEN "1001"=>LED7S6<="1101111"; WHEN "1010"=>LED7S6<="1110111"; WHEN "1011"=>LED7S6<="1111100"; WHEN "1100"=>LED7S6<="0111001"; WHEN "1101"=>LED7S6<="1011110"; WHEN "1110"=>LED7S6<="1111011"; 11 WHEN "1111"=>LED7S6<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q7:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN Q7:=Q(24)&Q(25)&Q(26)&Q(27); CASE Q7 IS WHEN "0000"=>LED7S7<="0111111"; WHEN "0001"=>LED7S7<="0000110"; WHEN "0010"=>LED7S7<="1011011"; WHEN "0011"=>LED7S7<="1001111"; WHEN "0100"=>LED7S7<="1100110"; WHEN "0101"=>LED7S7<="1101101"; WHEN "0110"=>LED7S7<="1111101"; WHEN "0111"=>LED7S7<="0000111"; WHEN "1000"=>LED7S7<="1111111"; WHEN "1001"=>LED7S7<="1101111"; WHEN "1010"=>LED7S7<="1110111"; WHEN "1011"=>LED7S7<="1111100"; WHEN "1100"=>LED7S7<="0111001"; WHEN "1101"=>LED7S7<="1011110"; WHEN "1110"=>LED7S7<="1111011"; WHEN "1111"=>LED7S7<="1110001"; WHEN OTHERS=> NULL; END CASE; END PROCESS; PROCESS(Q) VARIABLE Q8:STD_LOGIC_VECTOR(3 DOWNTO 0); 12 BEGIN Q8:=Q(28)&Q(29)&Q(30)&Q(31); CASE Q8 IS WHEN "0000"=>LED7S8<="0111111"; WHEN "0001"=>LED7S8<="0000110"; WHEN "0010"=>LED7S8<="1011011"; WHEN "0011"=>LED7S8<="1001111"; WHEN "0100"=>LED7S8<="1100110"; WHEN "0101"=>LED7S8<="1101101"; WHEN "0110"=>LED7S8<="1111101"; WHEN "0111"=>LED7S8<="0000111"; WHEN "1000"=>LED7S8<="1111111"; WHEN "1001"=>LED7S8<="1101111"; WHEN "1010"=>LED7S8<="1110111"; WHEN "1011"=>LED7S8<="1111100"; WHEN "1100"=>LED7S8<="0111001"; WHEN "1101"=>LED7S8<="1011110"; WHEN "1110"=>LED7S8<="1111011"; WHEN "1111"=>LED7S8<="1110001"; WHEN OTHERS=> NULL; END CASE;END PROCESS; END four; 仿真结果: 13 4.顶层模块 为了达到连接底层元件形成更高层次的电路设计结构，设计中使用了例化语句 程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FRE8 IS PORT( CLK :IN STD_LOGIC; fin :IN STD_LOGIC; LED7S1,LED7S2,LED7S3,LED7S4,LED7S5,LED7S6,LED7S7,LED7S8:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END FRE8; ARCHITECTURE bhv8 OF FRE8 IS COMPONENT FIC1 PORT (CLK1:IN STD_LOGIC; CNT: OUT STD_LOGIC; RST:OUT STD_LOGIC; LOAD:OUT STD_LOGIC); 14 END COMPONENT; COMPONENT CNT32 PORT (CLR:IN STD_LOGIC; EN:IN STD_LOGIC; fin:IN STD_LOGIC; COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; COMPONENT REG32A PORT( LK :IN STD_LOGIC; DIN :IN STD_LOGIC_VECTOR (31 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); END COMPONENT; COMPONENT DECL7S PORT (Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0); LED7S1,LED7S2,LED7S3,LED7S4,LED7S5,LED7S6, LED7S7,LED7S8:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END COMPONENT; SIGNAL a,b,c:STD_LOGIC; SIGNAL d,e: STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN u1 : FIC1 PORT MAP(CLK1=>CLK,CNT=>a,RST=>b,LOAD=>c); u2 : CNT32 PORT MAP(FIN=>fin,EN=>a,CLR=>b,COUT=>d); u3 : REG32A PORT MAP(LK=>c,DIN=>d,DOUT=>e); u4:DECL7SPORTMAP(Q=>e,LED7S1=>LED7S1,LED7S2=>LED7S2,LED7S3=>LED 7S3,LED7S4=>LED7S4,LED7S5=>LED7S5,LED7S6=>LED7S6,LED7S7=>LED7S7, LED7S8=>LED7S8); END ARCHITECTURE bhv8; 仿真结果: 15 总体设计电路图: 四 .总结 16 8位十六进制频率计是一种用十六进制数字显示被测信号频率的数字测量仪器。设计中利用了有层次结构的VHDL程序，采用了元件例化方法。用设计的电路原理图写出各模块的VHDL描述，再写出顶层VHDL描述。其中包含四个模块(控制模块、计数模块、锁存模块、显示模块)和一个顶层文件。控制模块用于产生测量频率的控制时序; 计数模块以待测信号作为时钟,清零信号rst到来时,异步清零;cnt-en为高电平时开始计数;锁存模块用于当cnt-en下降沿到来时，将计数器的计数值锁存，这样可由显示模块译码并在数码管显示;8位十六进制频率计的基本功能是测量正弦信号.方波信号,尖脉冲信号及其他各种单位时间内变化的物理量. 为了达到连接底层元件形成更高层次的电路设计结构，设计中使用了例化语句。文件在实体中首先定义了顶层设计元件的端口信号，再声明调用元件，并定义了信号a、b、c、d、e作为内部连接线，最后利用端口映射语句PORT MAP()将各模块连接起来。元件例化是使VHDL设计实体构成自上而下层次化设计的一种重要要途径。 五(参考文献 [1] 潘松 黄继业 EDA技术实用教程(M) 科学出版社 2006 [2] 李洪伟 袁斯华 EDA工具应用从(M)电子工业出版社 2006 17 18