SPCE061A 32K x 16 语音控制器--外文翻译(语音控制器)

SPCE061A 32K x 16 语音控制器--外文翻译(语音控制器) 沈阳航空航天大学毕业设计,外文翻译, SPCE061A 32K x 16 SOUND CONTROLLER 1. GENERAL DESCRIPTION The SPCE061A, a 16-bit architecture product, carries the newest 16-bit microprocessor, μ’nSP? (pronounced as micro-n-SP), developed by Sunplus Technology. This high processing speed assures the μ’nSP? is capable of handling complex digital signal processes easily and rapidly. Therefore, the SPCE061A is applicable to the areas of digital sound process and voice recognition. The operating voltage of 3.0V through 3.6V and speed of 0.32MHz through 49.152MHz yield the SPCE061A to be easily used in varieties of applications. The memory capacity includes 32K-word flash memory plus a 2K-word working SRAM. Other features include 32 programmable multi-functional I/Os, two 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Reset/Detection, eight channels 10-bit ADC (one channel built-in MIC amplifier with auto gain controller), 10-bit DAC output and many others. BLOCK DIAGRAM 3. FEATURES ? 16-bit μ’nSP? microprocessor ? CPU clock: 0.32MHz - 49.152MHz ? Operating voltage: 3.0V - 3.6V ? Program Flash Operating voltage: 3.0V - 3.6V ? IO PortA & B operating voltage: 3.0V - 5.5V ? 32K-word flash memory 1 沈阳航空航天大学毕业设计,外文翻译, ? 2K-word working SRAM ? Software-based audio processing ? Crystal Resonator ? Standby mode (Clock Stop mode) for power savings, Max. 2.0μA @ VDD = 3.6V ? Two 16-bit timers/counters ? Two 10-bit DAC outputs ? 32 general I/Os (bit programmable) ? 14 INT sources with two priority levels ? Key wakeup function (IOA0 - 7) ? Approx. 190 sec speech @ 2.0Kbit/per sec with SACM_S200 ? PLL feature for system clock ? 32768Hz Real Time Clock (RTC) ? Eight channels 10-bit AD converter ? ADC external top reference voltage ? 2.0V voltage regulator output, 5mA of driving capability ? Serial interface I/O (SIO) ? Built-in microphone amplifier and AGC function ? UART receiver and transmitter (full duplex) ? Low voltage reset and low voltage detection ? Watchdog enable (bonding option) ? ICE function for development and down load into flash memory ? Security function to protect code to be read and written. 4. APPLICATION FIELD ? Voice recognition products ? Intelligent interactive talking toys ? Advanced educational toys ? Kids learning products ? Kids storybook ? General speech synthesizer ? Long duration audio products ? Recording / playback products SIGNAL DESCRIPTIONS 2 沈阳航空航天大学毕业设计,外文翻译, 5. FUNCTIONAL DESCRIPTIONS 5.1. CPU The SPCE061A is equipped with a 16-bit μ’nSP?, the newest 16-bit microprocessor by P. Eight registers are involved in μ’nSP?: R1 - R4 Sunplus and pronounced as micro-n-S (General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software-interrupt, BREAK. Moreover, a high performance hardware multiplier with the capability of FIR filter is also built in to reduce the software multiplication loading. 5.2. Memory 5.2.1. SRAM The amount of SRAM is 2K-word (including Stack), ranged from $0000 through $07FF with access speed of two CPU clock cycles. 5.2.2. Flash memory Flash memory ($008000 ~ $00FFFF) is a high-speed memory with access speed of two CPU 3 沈阳航空航天大学毕业设计,外文翻译, clock cycles. FLASH erase and program functions must be used in IDE tools. 5.3. PLL, Clock, Power Mode 5.3.1. PLL (Phase Lock Loop) The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from 20.48MHz to 49.152MHz for system clock (Fosc). The default PLL frequency is 24.576MHz. 5.3.1.1. System clock Basically, the system clock is provided by PLL and programmed by the Port_SystemClock (W) to determine the frequency of clock for system. The default system clock Fosc = 24.576MHz and CPU clock is Fosc/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and to be adjusted to desired CPU clock by programming the Port_SystemClock (W). This avoids Flash ROM reading failure when system wakes up. 5.3.1.2. 32768Hz RTC The Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2Hz-RTC (1/2 second) function is loaded in SPCE061A. The RTC counts the timing as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be traced by the numbers of RTC occurrence. In addition, SPCE061A supports 32768Hz oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always runs at the highest power consumption. In auto-power-saving mode, however, it runs in normal mode for the first 7.5 seconds and changes back to power-saving mode automatically to save powers. 5.4. Standby Mode The SPCE061A also offers a standby mode for low power application needs. To enter standby mode, the desired key wakeup port (IOA [7:0]) must be configured to input first. And read the Port_IOA_Latch(R) to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing the STOP CLOCK Register (b0~b2 of Port_SystemClock (W)) to enter standby mode. In such mode, SRAM and I/Os remain in the previous states till CPU being awoken. The wakeup sources in SPCE061A include Port IOA7 - 0 and IRQ1 - IRQ6. After SPCE061A is awoken, the CPU will continue to execute the program. Programmer can also enable or disable the 32768Hz OSC when CPU is in standby mode. 5.5. Low Voltage Detection and Low Voltage Reset 5.5.1. Low voltage detection (LVD) There are two LVD levels to be selected: 2.9V, and 3.3V. These levels can be programmed via Port_LVD_Ctrl (W). As an example, suppose LVD is given to 2.9V. When the voltage drops 4 沈阳航空航天大学毕业设计,外文翻译, below 2.9V, the b15 of Port_LVD_Ctrl is read as HIGH. In such state, program can be designed to react to this condition. 5.5.2. Low voltage reset In addition to the LVD, the SPCE061A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below 2.3V for 10 consecutive CPU clock cycles. Without LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below 2.3V. The LVR will reset all functions to the initial operational (stable) states when the voltage drops below 2.3V. A LVR timing diagram is given as follows: 5.6. Interrupt The SPCE061A has 14 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt while IRQ is the low-priority one. An IRQ can be interrupted by a FIQ, but not by another IRQ. A FIQ cannot be interrupted by any other interrupt sources. 5 沈阳航空航天大学毕业设计,外文翻译, 5.7. I/O Two I/O ports are built in SPCE061A, PortA and PortB. The PortA is an ordinary I/O with programmable wakeup capability. In addition to the regular IO function, the PortB can also perform some special functions in certain pins. Suppose operating voltage is running at 3.6V (VDD) and VDDIO (power for I/O) operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad is capable of operating from 0V through VDDIO. However IOB13 and IOB14 are recommended to operate <=3.6V during standby mode, otherwise these two IOs will have current leakage. The following diagram is an I/O schematic. Although data can be written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port. To activate key wakeup function, latch data on PORT_IOA_Latch and enable the key wakeup function. Wakeup is triggered when the PortA state is different from at the time latched. In addition to an ordinary I/O port, PortB carries some special functions. A summary of PortB special functions is listed as follows: 6 沈阳航空航天大学毕业设计,外文翻译, Refer to the above table, the configuration of IOB2, IOB3, IOB4, and IOB5 involves feedback function in which an OSC frequency can be obtained from EXT1 (EXT2) by simply adding a RC circuit between IOB2 (IOB3) and IOB4 (IOB5). 5.8. Timer / Counter The SPCE061A provides two 16-bit timers/counters, TimerA and TimerB. The TimerA is called a universal counter. TimerB is a general-purpose counter. The clock source of TimerA comes from the combination of clock source A and clock source B. In TimerB, the clock source is given from source C. When timer overflows, an INT signal is sent to CPU to generate a time-out signal. Initially, write a value of N into a timer and select a desired clock source, timer will start counting from N, N+1, N+2, ... through FFFF. An INT (TimerA/TimerB) signal is generated at the next clock after reaching “FFFF” and the INT signal is transmitted to INT controller for further processing. At the same time, N will be reloaded into timer and start all over again. The clock source A is a high frequency source and clock source B is a low frequency source. The combination of clock source A and B provides a variety of speeds to TimerA. A “1” represents pass signal and not gating. In contrast, “0” indicates deactivating timer. The EXT1 and EXT2 are the external clock sources. Moreover, counter can generate time-out signal for input clock source to a four bits (16 levels) PWM pulse width counter. A variety of clock duration can be generated and exported from IOB8 (APWMO) and IOB9 (BPWMO). 7 沈阳航空航天大学毕业设计,外文翻译, The following example is a 3/16-duration cycle. The APWMO waveform is made by selecting a pulse width through Port_TimerA_Ctrl (W) [9:6]. As a result, each 16 cycles will generate a pulse width defined in control port. These PWM signals can be applied for controlling the speed of motor or other devices. Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC system (32768Hz). Therefore, clock source B can be utilized as a precise counter for time counting, e.g., the 2Hz clock can be used for real time counting. 5.8.1. Timebase Timebase, generated by 32768Hz, is a combination of frequency selections. The outputs of timebase block are named to TMB1 and TMB2. TMB1 is frequency for TimerA (Clock source B). The TMB1 and TMB2 are the sources for Interrupt (IRQ6). Furthermore, timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC). 5.9. Sleep, Wakeup and Watchdog 5.9.1. Wakeup and sleep 1) Sleep: After power-on reset, IC starts running until a sleep command occurs. When a sleep command is accepted, IC will turn the system clock (PLL) off. After all, it enters sleep mode. 2) Wakeup: CPU waking up from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The IRQ signal makes CPU to complete the wakeup process and initialization. The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources. 5.9.2. Watchdog The purpose of watchdog is to monitor if the system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assumes the program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and 8 沈阳航空航天大学毕业设计,外文翻译, start running the program all over again. The watchdog function can be removed by bonding option. In SPCE061A, the clear period is 0.75 seconds. If watchdog is cleared within each 0.75 seconds, the system will not be reset. To clear watchdog, simply write “xxxx xxxx xxxx xx01B” to Port_Watchdog_Clear(W). The content written to Port_Watchdog_Clear(W) for watchdog clearance must be exactly the same as the one illustrated above (xxxx xxxx xxxx xx01B). Other values given to the Port_Watchdog_Clear(W) for watchdog clearance may end up with system reset. The watchdog function remains enabled during standby mode if the 32768Hz is turned on. 5.10. ADC (Analog to Digital Converter) / DAC The SPCE061A has eight channels 10-bit ADC (Analog to Digital Converter). The function of an ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word. The eight channels of ADC can be seven channels of line-in from IOA [6:0] or one channel microphone (MIC) input through amplifier and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. The ADC is able to choose the external or internal (=AVDD) top reference voltage. If constant voltage source is unavailable, SPCE061A offers a constant voltage 2.0V with 5.0mA driving ability with a capacitor connected. The SPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving current for audio outputs, DAC1 and DAC2. 5.11. Serial Interface I/O (SIO) Serial interface I/O offers a one-bit serial interface for communication. This serial interface is capable of transmitting or receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA). 5.12. UART UART block provides a full-duplex standard interface that facilitates the communication with other devices. With this interface, SPCE can transmit and receive simultaneously. The maximum 9 沈阳航空航天大学毕业设计,外文翻译, baud-rate can be up to 115200bps. This function can be accomplished by using PortB and Interrupt (UART IRQ). The Rx and Tx of UART are shared with IOB7 and IOB10. When SPCE061A receives and/or transmits a frame of data, the b7 (RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be set to “1” and the UART IRQ is activated at the same time. 10 沈阳航空航天大学毕业设计,外文翻译, SPCE061A 32K x 16 语音控制器 1. 总述 SPCE061A 是继μ’nSP?系列产品SPCE500A等之后凌阳科技推出的又一个16位结构的微控制器。与SPCE500A不同的是，在存储器资源方面考虑到用户的较少资源的需求以及便于程序调试等功能，SPCE061A里只内嵌32K字的闪存FLASH ROM。较高的处理速度使μ’nSP?能够非常容易地、快速地处理复杂的数字信号。因此，与SPCE500A相同，以μ’nSP?为核心的SPCE061A微控制器也适用在数字语音识别应用领域。 SPCE061A在2.6V~3.6V电压范围内的工作速度范围为0.32MHz~49.152MHz，较高的工作速度使其应用领域更加拓宽。2K字SRAM和32K字闪存ROM仅占一页存储空间，32位可编程的多功能I/O端口;两个16位定时器/计数器;32768Hz实时时钟;低电压复位/监测功能;8通道10位模-数转换输入功能并具有内置自动增益控制功能的麦克风输入方式;双通道10位DAC方式的音频输出功能。SPCE061A是数字声音和语音识别产品的一种最经济的应用。 2. 性能 • 16位μ’nSP?微处理器; • 工作电压:VDD为2.6~3.6V(cpu), VDDH为VDD~5.5V(I/O); • CPU时钟:0.32MHz~49.152MHz ; • 内置2K字SRAM; • 内置32K闪存ROM; • 可编程音频处理; • 晶体振荡器; • 系统处于备用状态下(时钟处于停止状态)，耗电小于2μA@3.6V; • 2个16位可编程定时器/计数器(可自动预置初始计数值); • 2个10位DAC(数-模转换)输出通道; • 32位通用可编程输入/输出端口; • 14个中断源可来自定时器A / B，时基，2个外部时钟源输入，键唤醒; • 具备触键唤醒的功能; • 使用凌阳音频编码SACM_S240方式(2.4K位/秒)，能容纳210秒的语音数据; • 锁相环PLL振荡器提供系统时钟信号; • 32768Hz实时时钟; 1 沈阳航空航天大学毕业设计,外文翻译, • 7通道10位电压模-数转换器(ADC)和单通道声音模-数转换器 • 声音模-数转换器输入通道内置麦克风放大器和自动增益控制(AGC)功能; • 具备串行设备接口; • 低电压复位(LVR)功能和低电压监测(LVD)功能; • 内置在线仿真板(ICE，In- Circuit Emulator)接口。 3. 结构框图 SPCE061A的结构如下图3.1所示: 图3.1 4. 应用领域 • 语音识别类产品 • 智能语音交互式玩具 • 高级亦教亦乐类玩具 • 儿童电子故事书类产品 • 通用语音合成器类产品 • 需较长语音持续时间类产品 5. 功能描述 5.1. CPU SPCE061A配备了凌阳科技开发的最新的16位微处理器μ’nSP?。它内含有8个寄存器:4个通用寄存器R1~R4，1个程序计数器PC，1个堆栈指针SP，1个基址指针BP和1个段寄存器SR。通用寄存器R3和R4结合形成一个32位寄存器MR，MR可被用作乘法运算和内积运算的目标寄存器。此外，SPCE061A有3个FIQ中断和14个IRQ中断，并且带有一个由指令BREAK控制的软中断。 μ’nSP?不仅可以进行加、减等基本算术运算和逻辑运算，还可以完成用于数字信号处理的乘法运算和内积运算。 2 沈阳航空航天大学毕业设计,外文翻译, 5.2. 存储器 5.2.1. RAM SPCE061A拥有2K字的SRAM(包括堆栈区)，其地址范围从$000000到$0007FF。 5.2.2. 闪存(Flash)ROM 全部32K字闪存均可在ICE工作方式下被编程写入或被擦除。对闪存设置保密设定后，其内容将不能再通过ICE被读写，也就可以使程序不被其他人读取。 5.3. 时钟(锁相环振荡器，系统时钟，实时时钟) 5.3.1. 锁相环(PLL，Phase Lock Loop)振荡器 PLL的作用是为系统提供一个实时时钟的基频(32768Hz)，然后将基频进行倍频，调整至49.152MHz、40.96MHz、32.768MHz、24.576MHz或20.480MHz。系统默认的PLL自激振荡频率为24.576MHz。 PLL的结构如下图5.1所示: 图5.1 5.3.2. 时钟 5.3.2.1. 系统时钟 系统时钟的信号源为PLL振荡器。系统时钟频率(Fosc)和CPU时钟频率(CPUCLK)可通过对P_SystemClock(写)($7013H)单元编程来控制。默认的Fosc、CPUCLK分别为24.576MHz和Fosc/8。用户可以通过对P_SystemClock单元编程完成对系统时钟和CPU时钟频率的定义。当系统被唤醒后最初时刻的CPUCLK频率亦为Fosc/8，随后逐渐被调整到用户设定的CPUCLK频率。这样，可避免系统在唤醒初始时刻读ROM出现错误。 5.3.2.2. 实时时钟(32768Hz) 32768Hz实时时钟通常用于钟表、实时时钟延时以及其它与时间相关类产品。SPCE061A通过对32768Hz实时时钟源分频而提供了多种实时时钟中断源。例如，用作唤醒源的中断源IRQ5_2Hz，表示系统每隔0.5秒被唤醒一次，由此可作为精确的计时基准。” 除此之外，SPCE061A 还支持RTC振荡器强振模式/自动模式的转换。处于强振模式时，RTC振荡器始终运行在高耗能的状态下。处于自动弱振模式时，系统在上电复位后的前7.5s内处于强振模式，然后自动切换到弱振模式以降低功耗。 下图5.2为SPCE061A与晶体振荡器的连接电路原理图。 3 沈阳航空航天大学毕业设计,外文翻译, 图5.2 5.4. 节电模式 SPCE061A可设置节电的备用模式以达到节能的目的。在这种工作模式下，只需很小(小于2μA)的备用电流。 要进入待命工作模式，首先应将所需的键唤醒口IOA[7~0]设为输入端口。在进入待命工作模式前，通过读P_IOA_Latch单元来激活IOA[7~0]口的唤醒功能，或者允许作为唤醒源的中断源中断请求的响应;然后通过写入P_SystemClock单元一个CPUClk STOP控制字(CPU睡眠信号)，以停止CPUClk工作，进入‘睡眠’状态。P_SystemClock单元还可用来编程设置在CPU进入‘睡眠’时是禁止允许32768Hz实时时钟的工作。 / 在待命模式下，RAM和I/O端口的状态都将维持进入‘睡眠’前的各个状态，直到产生‘唤醒’信号。SPCE061A的唤醒源包括键唤醒IOA[7~0]端口以及各中断源(IRQ0 ~ IRQ6)。当SPCE061A的CPU被唤醒后，会继续执行程序指令。 5.5. 低电压监测和低电压复位 5.5.1. 低电压监测 (LVD，Low Voltage Detect) 低电压监测功能可以提供系统内电源电压的使用情况。4级电压监测低限:2.4V、2.8V、3.2和3.6V，可通过对P_LVD_Ctrl单元编程进行控制。假定VLVD=3.2V，当系统电压Vcc低于3.2V时，P_LVD_Ctrl单元的第15位返回值为“1”，这样，CPU可以通过可编程电压监测低限来完成低电压监测。系统默认的电压监测低限为2.4V。 5.5.2. 低电压复位 (LVR，Low Voltage Reset) 引起SPCE061A复位通常有2个途径:电源上电复位、低电压复位(LVR)。 当电源电压低于2.2V时，系统会变得不稳定且易出故障。导致电源电压过低的原因很多，如电压的反跳、负载过重、电池能量不足„„。如果系统设置了低电压复位(LVR)功能，当电源电压低于该值时，会在4个时钟周期之后产生一个复位信号，使系统复位。如下图5.3: 4 沈阳航空航天大学毕业设计,外文翻译, 图5.3 5.6. 中断(Interrupt) SPCE061A具有两种中断方式:快速中断请求FIQ(Fast Interrupt Request) 中断和中断请求IRQ(Interrupt Request)中断。中断控制器可处理3种FIQ中断和14种IRQ中断，以及一个由指令BREAK控制的软中断。 相比之下，FIQ中断的优先级较高而IRQ中断的优先级较低。也就是说，FIQ中断可以中断IRQ中断服务子程序的执行，而CPU执行相应的FIQ中断服务子程序的过程不能被任何中断源的中断请求中断。下表1列出了中断的优先级别: 表1 5.7. 输入/输出端口(I/O，Input/Output) 输入输出端口是系统与其它设备进行数据交换的接口。SPCE061A具有两个可编程输入输出端口:A口和B口。A口既是具有可编程唤醒功能的普通I/O口，又可与ADC的多路LINE_IN输入共用(IOA[6~0]与LINE_IN[1~7]共用;B口除了具有普通I/O口的功能外，在特定的管脚上还可以完成一些特殊的功能。I/O端口如下图5.4所示: 5 沈阳航空航天大学毕业设计,外文翻译, 图5.4 尽管数据能通过数据端口P_IOX_Data和数据缓冲器端口P_IOX_Buffer写入相同的数据寄存器，但从这两个端口读出的数据却来自不同的位置;从后者读出的仍是数据寄存器里的数据，而从前者读出的是I/O管脚上的电平状态。IOA[7~0]口为键唤醒源，通过读P_IOA_Latch单元来锁存IOA[7~0]端口的电平状态，从而可激活其唤醒功能。当IOA[7~0]口的状态和锁存时的状态不一致时，会触发系统由节电的睡眠工作模式切换到唤醒模式。 B口除了具有常规的输入/输出端口功能外，还有一些特殊的功能，如下表2所示: 表2 如下图5.5所示的电路显示了带有反馈应用的IOB2、IOB3、IOB4和IOB5等端口的设置情况。有了反馈功能，只要在IOB2(IOB3)和IOB4(IOB5)之间增加一个RC电路就可以从EXT1 (EXT2)得到振荡源频率信号。 6 沈阳航空航天大学毕业设计,外文翻译, 图5.5 5.8. 定时器/计数器(Timer/Counter) SPCE061A提供了两个16位的定时器/计数器:TimerA和TimerB。TimerA为通用计数器;TimerB为多功能计数器。TimerA的时钟源由时钟源A和时钟源B进行“与”操作而形成;TimerB的时钟源仅为时钟源A。定时器发生溢出后会产生一个溢出信号(TAOUT/TBOUT)。一方面，它会作为定时器中断信号传输给CPU中断系统;另一方面，它又会作为4位计数器计数的时钟源信号，输出一个具有4位可调的脉宽调制占空比输出信号APWMO或BPWMO(分别从IOB8 和IOB9输出)，用来控制马达或其它一些设备的速度。此外，定时器溢出信号还可以用于触发ADC输入的自动转换过程和DAC输出的数据锁存。 表3 向定时器的P_TimerA_Data(读/写)($700AH)单元或P_TimerB_Data(读/写)($700CH)单元写入一个计数值N后，选择一个合适的时钟源，定时器/计数器将在所选的时钟频率下开始以递增方式计数N，N+1，N+2，„0xFFFE，0xFFFF。当计数达到0xFFFF后，定时器/计数器溢出，产生中断请求信号，被CPU响应后送入中断控制器进行处理。同时，N值将被重新载入定时器/计数器并重新开始计数。 在TimerA内，时钟源A是一个高频时钟源，时钟源B是一个低频时钟源。时钟源A和时钟源B的组合，为TimerA提供出多种计数速度。若以ClkA作为门控信号，‘1’表示允许时钟源B信号通过，而‘0’则表示禁止时钟源B信号通过而停止TimerA的计数。例如，如果时钟源A为“1”，TimerA时钟频率将取决于时钟源B;如果时钟源A为“0”，将停止TimerA的计数。EXT1和EXT2为外部时钟源。 7 沈阳航空航天大学毕业设计,外文翻译, 下图5.6为一个3/16的脉宽调制占空比输出信号产生过程的时序。APWMO波形是通过写入P_TimeA_Ctrl 单元的B9~B6选择一个脉宽数(以计数溢出周期数定义)产生出来的，即每16个计数溢出周期将产生一个由上述单元定义的脉宽。此类PWM信号可以用于控制马达及其它设备的速度。 图5.6 一般来说，时钟源A为高速时钟源，时钟源B来自实时时钟32678Hz系统。因此，时钟源B能用于一个精确的时间计数器。例如，2Hz 时钟信号可用于实时时间计数。 5.8.1. 时基 时间基准信号，简称时基信号，来自于32768Hz实时时钟，通过频率选择组合而成。时基信号发生器的2个选频逻辑TMB1和TMB2为TimerA的时钟源B提供各种频率选择信号并为中断系统提供中断源(IRQ6)信号。此外，时基信号发生器还可以直接生成2Hz、4Hz、1024Hz、2048Hz以及4096Hz的时基信号，为中断系统提供各种实时中断源(IRQ4和IRQ5)信号。 表4 5.9. 睡眠、唤醒 5.9.1. 睡眠与唤醒 1) 睡眠:IC在上电复位开始工作，直到接收到睡眠信号后，才关闭系统时钟(PLL振荡器)，进入睡眠状态。系统进入睡眠状态后，程序计数器(PC)会停在程序的下一条指令计数上，当有任一唤醒事件发生后开始由此继续执行程序。 2) 唤醒:若要将系统从睡眠状态唤醒，需要有唤醒源提供一个唤醒信号来启动系统时钟。IRQ中断请求信号引导CPU完成唤醒过程并将系统初始化。IRQ3_KEY为触键唤醒源(IOA7~0)，其它中断源(FIQ、IRQ1~IRQ6 及UART IRQ)都可以作为唤醒源。 5.10. 模数转换器 (ADC,Analog to Digital Converter) 与数/模转换器(DAC,Digital to Analog Converter) SPCE061A有8个10位模-数转换器通道，其中7个通道用于将模拟量信号 8 沈阳航空航天大学毕业设计,外文翻译, (例如电压信号) 转换为数字量信号, 可以直接通过引线(IOA[0~6])输入。另外有一个通道只作为语音输入通道，通过内置有自动增益控制放大器的麦克风通道(MIC_IN)输入。实际上可以把ADC看作是一个实现模/数信号转换的编码器。 SPCE061A为音频输出提供了两个10位的数-模转换器，即DAC1和DAC2。DAC1、DAC2转换输出的模拟量电流信号分别通过AUD1和AUD2管脚输出。 5.11. 串行设备接口(SIO，Serial Input Output) 串行输入输出端口SIO提供了一个1位的串行接口，用于与其它设备进行数据通讯。在SPCE061A内通过IOB0和IOB1这2个端口实现与设备进行串行数据交换功能。 5.12. 音频算法 在SPCE061A中可使用以下几种语音信号:PCM，LOG PCM，SACM_A3200，SACM_S240，SACM_S480，SACM_S720，SACM_A2000及SACM_A2000_DVR (Digital Voice Recorder)。至于音调合成，SPCE061A则提供了SACM_MS01 (FM synthesizer)和波表合成器。 5.13. 保密设定 如果希望将内部的闪存进行保密设定，可将PFUSE接5V, PVIN接GND并维持2s以上即可将内部保险丝熔化，此后就无法再完成download, debug等功能。 5.14. UART UART模块提供了一个全双工接口， 用于完成SPCE061A与外设之间的串行通讯(最大的波特率可达115200bps)。借助于IOB口的特殊功能和UART IRQ中断，可以完成UART接口的通讯功能。此外，SPCE061A还可以接收缓冲器内容。也就是说，它可以在读取缓存器内当前数据之前接收新的数据。但是，如果在新的数据接收完毕之前还没有从缓存器中读取当前数据，会发生数据丢失。P_UART_Data (读/写) ($7023H)单元可以用于接收和发送数据。向该单元写入数据，可以将发送的数据送入缓存器;从该单元读数据，可以从缓存器读出单个的数据。UART模块的接收管脚Rx和发送管脚Tx可分别与IOB7和IOB10共用。 内部资料， 请勿外传～ 精品资料精品资料 精品资料 精品资料 精品资料 9 沈阳航空航天大学毕业设计,外文翻译, 精品资料 型 号 , 制 造 厂 家 额定功率,KW, 560 额定电压,V, 400 额定电流,A, 1010 额定频率,Hz, 50 额定转速,r/min, 1500 功率因数 0.8,滞后, 励磁电流,A, 2 励磁电压,V, 40 定子绕组接线 Y 0 冷却方式 风冷 励磁方式 强励倍数2 绝缘等级 H 防护等级 蓄电池容量,Ah, 92 1 型 号 形 式 闭式循环水冷却、涡轮增压 额定功率,KW, 628 10 沈阳航空航天大学毕业设计,外文翻译, 额定转速,r/min, 1500 冷却方式 闭式循环水带热交换器 起动方式 24V直流电起动 燃油消耗,L,h, 保护与报警 定值与结果 保护与报警 定值与结果 过载 大于110%报警～大于120%延时5秒跳闸 出口电压高卸载 大于108% 短路 200%～延时0.08秒跳闸 出口电压低卸载 低于85% 电流不平衡 不平衡电流大于20%～延时5秒跳闸 电压高跳闸 大于110% 漏电电流 大于30%～延时10秒 三相电压不平衡 电压差大于10% 逆功率 大于8%～延时0.5秒 过频率 大于110% 超速 大于115%～延时5秒跳闸 低频率 小于85% 蓄电池电压低 小于21V 蓄电池电压高 大于30V 差动保护 0秒跳闸 失磁保护 跳闸 单相接地保护 跳闸 过电流保护 跳闸 润滑油压低 跳闸 三次自起动失败 发信并闭锁自起动 冷却水温高 发信 润滑油温度高 发信 机油油压过低 跳闸 机油油压低 发信 冷却水断水 跳闸 燃油量过低 发信 油箱油位低 发信 冷却水水位低 发信 HYQ,Z ? /? 11 沈阳航空航天大学毕业设计,外文翻译, 12 沈阳航空航天大学毕业设计,外文翻译, 常见故障 产生原因 解 决 办 法 燃油供应量不足 开大燃油调节阀 雾化介质过量 关小雾化介质调节阀 点火位置不当 重新调整点火位置 燃油压力不稳定 稳定燃油压力 雾化介质压力不稳定 稳定雾化介质压力 13 沈阳航空航天大学毕业设计,外文翻译, 雾化介质过量 关小雾化介质调节阀 喷头有异物堵塞 清理喷头 燃油压力低 增大燃油压力 雾化介质压力小 增大雾化介质压力 助燃风小 调大助燃风 燃油量大 关小燃油调节阀 火焰 助燃风小 调大助燃风 雾化介质少 增大雾化介质流量 燃油量少 增加燃油供应量 焰呈 助燃风大 减小助燃风 燃油中有杂质 管路中设置过滤器 漏油 接头密封不严 拧紧软管接头 14