ADSL电路图

Bb s.C hin adz .Co m IDT79RP351 ADSL Bridge/Router Reference Platform Manual November 2002 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2005 Integrated Device Technology, Inc. Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Bb s.C hin adz .Co m The IDT logo, Dualsync, Dualasnyc and ZBT are registered trademarks of Integrated Device Technology, Inc. IDT, QDR, RISController, RISCore, RC3041, RC3051, RC3052, RC3081, RC32134, RC32364, RC36100, RC4700, RC4640, RC64145, RC4650, RC5000, RC64474, RC64475, SARAM, Smart ZBT, SuperSync, SwitchStar, Terasync,Teraclock, are trade- marks of Integrated Device Technology, Inc. Powering What's Next and Enabling A Digitally Connected World are service marks of Integrated Device Technology, Inc. Q, QSI, SynchroSwitch and Turboclock are registered trade- marks of Quality Semiconductor, a wholly-owned subsidiary of Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or perfor- mance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement per- taining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351 Reference Bb s.C hin adz .Co m Table of Contents 1 IDT79RP351 Description and Requirements Introduction ..................................................................................................................................1-1 Revision History...........................................................................................................................1-1 Overview of Features...................................................................................................................1-2 System Overview.........................................................................................................................1-2 Hardware Description.........................................................................................................1-2 References ..................................................................................................................................1-3 2 Installation of IDT79RP351 Reference Platform 79RP351 Installation....................................................................................................................2-1 Getting Started Quickly................................................................................................................2-1 Power Connector (P1)........................................................................................................2-1 ADSL Connector (J2) .........................................................................................................2-2 Ethernet Connector (J14) ...................................................................................................2-2 USB Connector (J3) ...........................................................................................................2-2 EJTAG Connector (J1) .......................................................................................................2-3 CPU/DSL UART (J3)..........................................................................................................2-4 Jumper Information ............................................................................................................2-4 3 Theory of Operations and Design Notes Overview......................................................................................................................................3-1 Default Memory Map ...................................................................................................................3-1 Interrupt Assignments ........................................................................................................3-1 LEDs ............................................................................................................................................3-2 4 Software Programming Linux ............................................................................................................................................4-1 Running OpenRG from Jungo............................................................................................4-1 5 Schematics Schematics Errata .......................................................................................................................5-1 Revision History .................................................................................................................5-1 Platform Manual i November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Table of Contents IDT79RP351 Reference Notes Bb s.C hin adz .Co m Platform Manual ii November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351 Reference Bb s.C hin adz .Co m List of Tables Table 2.1 P1 Power Connectors.......................................................................................................2-1 Table 2.2 ADSL Connector J2 ..........................................................................................................2-2 Table 2.3 Ethernet Connector J14....................................................................................................2-2 Table 2.4 USB Connector J13 ..........................................................................................................2-2 Table 2.5 J1 EJTAG Connector ........................................................................................................2-3 Table 2.6 CPU/DSL UART J3...........................................................................................................2-4 Table 2.7 Jumper Information...........................................................................................................2-4 Table 3.1 Default Memory Map after Reset......................................................................................3-1 Table 3.2 External Interrupts ............................................................................................................3-2 Table 3.3 LEDs .................................................................................................................................3-2 Platform Manual iii November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com List of Tables IDT79RP351 Reference Notes Bb s.C hin adz .Co m Platform Manual iv November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351 Reference Bb s.C hin adz .Co m List of Figures Figure 1.1 ADSL Bridge/Router Board Block Diagram ......................................................................1-1 Figure 3.1 79RP351 Block Diagram ..................................................................................................3-1 Platform Manual v November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com List of Figures IDT79RP351 Reference Notes Bb s.C hin adz .Co m Platform Manual vi November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351 Reference Platform Manual 1 - 1 Novem Revision July 12, 2001: January 23, 2 SDRAM to 16MB added jumper J15. Free Datasheet Download http://www.Chinadz.Com History Initial publication. 002: Deleted Mechanical Requirements section, changed Flash memory to 4 MB and , switched pins 8 and 9 in Table 2.6, switched jumper pins J6 and J12 in Table 2.7 and Bb s.C hin adz .Co m Chapter 1 IDT79RP351 Description and Requirements Introduction The 79RP351 is a reference platform designed to demonstrate the capabilities of the RC32351 inte- grated processor for cost effective ADSL modem. In addition to the RC32351 integrated communications processor (ICP), the motherboard includes an ADSL wide area network (WAN) interface and both USB and Ethernet local area network (LAN) interfaces. The board is designed to be a production ready, turnkey plat- form that the customer can implement immediately. Schematics and board gerber files are available to enable customer to manufacture the board in a high volume environment. Figure 1.1 illustrates the block diagram for the 79RP351 ADSL modem board. The 79RP351 is based on the RC32351 ICP, which is the fourth member of IDT’s integrated micropro- cessor family developed to meet the needs of communications applications. This integrated communica- tions processor couples IDT's award-winning 32-bit RISCore™ 32300 CPU core [fully compatible with the MIPS instruction set architecture (ISA)] and IDT's IPBus system-level integration design methodology with a series of general-purpose and communications specific peripherals. The on-chip communications peripherals are: – A 10/100-Mbps Ethernet controller providing an industry standard MII interface off chip – An ATM segmentation and reassembly (SAR) controller supporting industry standard Utopia 1 and Utopia 2 bus – A Universal Serial Bus (USB) controller compatible with version 1.1 of the specification. A high-performance DMA engine on the RC32351 enables customers to move data in any format without restrictions, thus increasing the system flexibility and the software flexibility in manipulating the data and enabling the processor to handle data on all four communications interfaces concurrently. The RC32351 is ideally suited for a variety of CPE, from the simplest ADSL modems to higher-end resi- dential gateways that require voice support. The on-chip communication peripherals allow the customer the flexibility to connect to a variety of LAN and WAN peripherals. Figure 1.1 ADSL Bridge/Router Board Block Diagram Memory Control ATM USB Ethernet RC32351 4MB x16 Flash 16MB x32 SDRAM DSL Chipset Alcatel MTK-20150 Transceiver DSL Connector USB Device Connector Ethernet Connector ber 6, 2002 http://www.Icver.Com IDT79RP351 Description and Requirements Overview of Features IDT79RP351 Reference Notes Bb s.C hin adz .Co m March 20, 2002: Added new Chapter 4, Software Programming. November 6, 2002: Added Schematics Errata section to Chapter 5. Overview of Features ‹ RC32351 integrated processor operating at 133MHz ‹ 16MB of SDRAM (2Mx32) ‹ 2MB or 4MB of Flash (1Mx16 or 2Mx16) ‹ Ethernet connection ‹ USB connection ‹ RJ-11 DSL connector ‹ Alcatel MTK20150 chipset ‹ ICE / Debug Header ‹ RS-232 Serial port System Overview The aim of the 79RP351 platform is to provide a reference solution that provides a base set of hardware and software functions that will be needed in any system designed to address the needs of an ADSL modem product. Based on the RC32351, it includes interfaces out to an ADSL line, via an Alcatel MTK-20150 chipset, to an Ethernet LAN interface and to a USB interface. Hardware Description The 79RP351 provides an optimum solution for a gateway product that incorporates a DSL interface for access to the wide area network (WAN) and connection to an internal network of personal computers via both USB (in the case of a single PC environment) and Ethernet (single or multiple PCs connected). The following is a list of the features of the 79RP351 Reference design: ‹ RC32351 processor – Up to 133 MHz system bus frequency – SDRAM & Memory Controller – USB v1.1 compliant slave (device) controller – Ethernet w/ MII interface – ATM w/ Utopia I & II ‹ One 16 MByte SDRAM Micron 48LC4M32B2 or equivalent. ‹ One 48 Pin TSOP MERITEC Flash Memory Prototype Socket – 1Mx16 or 2Mx16, 3.3V Flash to reside in the socket. ‹ RS-232 interface with 2x5 Pin Serial Connection Header ‹ One Level One LXT972 3.3v 10/100 Mb/s TX/10BT Ethernet PHY – Eric Electronics Magnetic module 10/100 BASE-TX TG110_S050N2 or equivalent – RJ-45 Ethernet Jack ‹ Alcatel ADSL Dynamite MTK-20150 Modem Chipset – One MTC-20154 ADSL Analog Front End – One MTC-20156 ADSL DMT Transceiver with ATM Framer – One 1Mx16 SDRAM,8ns,3.3V Micron MT48LC1M16A1TG or equivalent – One Line Driver – One RJ-11 ADSL Connection Jack ‹ One AMP 787761-2 Series-B USB Receptacle ‹ ICE/Debug Header – 2 x 12 male header (pitch 1.27 x 1.27 mm) ‹ Reset Generation – Power on hard reset generation circuitry. – Push button hard reset generation circuit. Platform Manual 1 - 2 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com IDT79RP351 Description and Requirements References IDT79RP351 Reference Notes Bb s.C hin adz .Co m ‹ Power & Reset LEDs. ‹ One Power supply 12VDC @ 1.0A Wall-plug-in type from ELPAC model WP1212 or equivalent. References ‹ IDTRC32351 Integrated Communications Processor Hardware User’s Manual ‹ IDTRC32351 Integrated Communications Processor Data Sheet ‹ Level One LXT972 10/100 Mb/s TX/10BT Ethernet PHY Data Sheet ‹ IDT/sim 8.3 user manual. Platform Manual 1 - 3 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com IDT79RP351 Description and Requirements References IDT79RP351 Reference Notes Bb s.C hin adz .Co m Platform Manual 1 - 4 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351 Reference Platform Manual 2 - 1 Novem Free Datasheet Download http://www.Chinadz.Com Bb s.C hin adz .Co m Chapter 2 Installation of IDT79RP351 Reference Platform 79RP351 Installation The primary installation steps are as follows: 1. Connecting a power source – This involves connecting an external power supply to the board. 2. Configuring jumper options – This involves altering CPU reset initialization mode vector, etc. The board is shipped with the jumpers set to the default configuration. 3. Running software – No additional software required. Getting Started Quickly The 79RP351 board is shipped ready to run. Before the board is shipped, jumpers and switches are configured to the default settings, and generally they do not require further modification or set up. The board is designed to be used with an external power supply which is supplied with the board. Refer to ADSL modem software documentation (such as OpenRG from Jungo) for more information on system setup, including connections with ADSL traffic source, USB master device, and LANs. Power Connector (P1) PIN SIGNAL 1 + 12V 2 GND 3 GND Table 2.1 P1 Power Connectors ber 6, 2002 http://www.Icver.Com Installation of IDT79RP351 Reference Platform Getting Started Quickly IDT79RP351 Reference Notes Bb s.C hin adz .Co m ADSL Connector (J2) Ethernet Connector (J14) USB Connector (J3) PIN BOARD SIGNAL 1 NC 2 NC 3 TIP 4 TIP 5 RING 6 RING 7 NC 8 NC 9 GND 10 GND Table 2.2 ADSL Connector J2 PIN BOARD SIGNAL 1 TX+ 2 TX- 3 RX+ 4 5 6 RX- 7 8 9 GND 10 GND Table 2.3 Ethernet Connector J14 PIN BOARD SIGNAL 1 NC 2 D- 3 D+ 4 GND Table 2.4 USB Connector J13 Platform Manual 2 - 2 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Installation of IDT79RP351 Reference Platform Getting Started Quickly IDT79RP351 Reference Notes Bb s.C hin adz .Co m EJTAG Connector (J1) All even pins are GND. Pin Signal Description 1 TRST_N The TRST_N pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. 3 TDI On the rising edge of TCK, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG). 5 TDO The TDO is serial data shifted out from instruction or data register on the falling edge of Tclk. When no data is shifted out, the TDO is tri-stated. During Real Time Mode, this signal provides a non-sequential program counter at the pro- cessor clock or at a division of processor clock. 7 TMS The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising edge of the TCLK. 9 TCK An input test clock, used to shift into or out of the Boundary-Scan register cells. Tclk is independent of the system and the processor clock with nominal 50% duty cycle. 11 RSTN Reset input, an active low signal for asynchronous reset of the entire target board. 13 PCST0 PC Trace Status Information. 15 PCST1 111 (STL) Pipe line Stall. 110 (JMP) Branch/Jump forms with PC output. 17 PCST2 101 (BRT) Branch/Jump forms with no PC output 100 (EXP) Exception generated with an exception vector code output 011 (SEQ) Sequential performance 010 (TST) Trace is outputted at pipeline stall time 001 (TSQ) Trace trigger output at performance time 000 (DBM) Run Debug Mode During power-on reset (cold reset), PCST(2:0) serves as Mode Bit(2:0). 19 DCLK Processor Clock. During Real Time Mode, this signal is used to capture address and data from the TDO signal at the processor clock speed, or any divi- sion of the internal pipeline. DCLK will be at 1/3 of the pipeline clock. 21 DEBUG BOOT The Debugboot input is used during the reset and forces the CPU core to take a debug exception at the end of the reset sequence instead of a reset exception. This enables the CPU to boot from the ICE probe without having the external memory working. This input signal is level sensitive and is not latched internally. 23 Vcc I/O Table 2.5 J1 EJTAG Connector Platform Manual 2 - 3 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Installation of IDT79RP351 Reference Platform Getting Started Quickly IDT79RP351 Reference Notes Bb s.C hin adz .Co m CPU/DSL UART (J3) Jumper Information Pin Signal 1 NC 2 UART-TX0 3 UART- RX0 4 NC 5 GND 6 GND 7 NC 8 RS - TXD (DSL) 9 RS - RXD (DSL) 10 NC Table 2.6 CPU/DSL UART J3 J4 DSL loopback J5 Flash write protect (write enabled when jumper is in place) J6 Boot config 1-2 GPIO[31, 13:10] behaves as GPIO 2-3 GPIO [31, 13:10] behaves as EJTAG J12 Boot config 1-2 Little Endian 2-3 Big Endian J15 Download 1-2 Serial 2-3 Parallel Table 2.7 Jumper Information Platform Manual 2 - 4 November 6, 2002 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com Notes IDT79RP351